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the FPRs with no conversion. Load Single instructions
are provided to transfer and convert floating-point values
in floating-point single format from storage to the
same value in floating-point double format in the FPRs.
Store Single instructions are provided to transfer and
convert floating-point values in floating-point double
format from the FPRs to the same value in floating-point
single format in storage.
Instructions are provided that manipulate the Floating-Point
Status and Control Register and the Condition
Register explicitly. Some of these instructions copy
data from an FPR to the Floating-Point Status and Control
Register or vice versa.
The computational instructions and the Select instruction
accept values from the FPRs in double format. For
single-precision arithmetic instructions, all input values
must be representable in single format; if they are not,
the result placed into the target FPR, and the setting of
status bits in the FPSCR and in the Condition Register
(if Rc=1), are undefined.
FPR 0
FPR 1
. . .
. . .
FPR 30
FPR 31
0 63
Figure 43. Floating-Point Registers
4.2.2 Floating-Point Status and
Control Register
The Floating-Point Status and Control Register
(FPSCR) controls the handling of floating-point exceptions
and records status resulting from the floating-point
operations. Bits 32:55 are status bits. Bits
56:63 are control bits.
The exception bits in the FPSCR (bits 35:44, 53:55) are
sticky; that is, once set to 1 they remain set to 1 until
they are set to 0 by an mcrfs, mtfsfi, mtfsf, or mtfsb0
instruction. The exception summary bits in the FPSCR
(FX, FEX, and VX, which are bits 32:34) are not considered
to be “exception bits”, and only FX is sticky.
FEX and VX are simply the ORs of other FPSCR bits.
Therefore these two bits are not listed among the
FPSCR bits affected by the various instructions.
FPSCR
32 63
Figure 44. Floating-Point Status and Control
Register
The bit definitions for the FPSCR are as follows.
Bit(s) Description
32 Floating-Point Exception Summary (FX)
Every floating-point instruction, except mtfsfi
and mtfsf, implicitly sets FPSCR FX to 1 if that
instruction causes any of the floating-point
exception bits in the FPSCR to change from 0
to 1. mcrfs, mtfsfi, mtfsf, mtfsb0, and
mtfsb1 can alter FPSCR FX explicitly.
Programming Note
FPSCR FX is defined not to be altered
implicitly by mtfsfi and mtfsf because
permitting these instructions to alter
FPSCR FX implicitly could cause a paradox.
An example is an mtfsfi or mtfsf
instruction that supplies 0 for FPSCR FX
and 1 for FPSCR OX , and is executed
when FPSCR OX =0. See also the Programming
Notes with the definition of
these two instructions.
33 Floating-Point Enabled Exception Summary
(FEX)
This bit is the OR of all the floating-point
exception bits masked by their respective
enable bits. mcrfs, mtfsfi, mtfsf, mtfsb0, and
mtfsb1 cannot alter FPSCR FEX explicitly.
34 Floating-Point Invalid Operation Exception
Summary (VX)
This bit is the OR of all the Invalid Operation
exception bits. mcrfs, mtfsfi, mtfsf, mtfsb0,
and mtfsb1 cannot alter FPSCR VX explicitly.
35 Floating-Point Overflow Exception (OX)
See Section 4.4.3, “Overflow Exception” on
page 101.
36 Floating-Point Underflow Exception (UX)
See Section 4.4.4, “Underflow Exception” on
page 102.
37 Floating-Point Zero Divide Exception (ZX)
See Section 4.4.2, “Zero Divide Exception” on
page 101.
38 Floating-Point Inexact Exception (XX)
See Section 4.4.5, “Inexact Exception” on
page 103.
FPSCR XX is a sticky version of FPSCR FI (see
below). Thus the following rules completely
describe how FPSCR XX is set by a given
instruction.
If the instruction affects FPSCR FI , the
new value of FPSCR XX is obtained by
ORing the old value of FPSCR XX with
the new value of FPSCR FI .
If the instruction does not affect
FPSCR FI , the value of FPSCR XX is
unchanged.
Chapter 4. Floating-Point Processor [Category: Floating-Point]
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