Power ISA™ Version 2.03 - Power.org

Version 2.03
5.9 Fixed-Point Logical, Bit, and Move Instructions
The Logical instructions perform bit-parallel operations
on 64-bit operands. The Bit instructions manipulate a
bit, or create a bit mask, in a register. The Move instructions
move a register or an immediate value into a register.
The X-form Logical instructions with Rc=1, the SCI8-
form Logical instructions with Rc=1, the RR-form Logical
instructions with Rc=1, the e_and2i. instruction,
and the e_and2is. instruction set the first three bits of
CR field 0 as the arithmetic instructions described in
Section 5.5, “Fixed-Point Arithmetic Instructions”. (Also
see Section 4.1.1.) The Logical instructions do not
change the SO, OV, and CA bits in the XER.
The fixed-point Logical instructions from Book I, and[.],
or[.], xor[.], nand[.], nor[.], eqv[.], andc[.], orc[.],
extsb[.], extsh[.], cntlzw[.], and popcntb are available
while executing in VLE mode. The mnemonics,
decoding, and semantics for these instructions are
identical to those in Book I; see Section 3.3.12 of Book
I for the instruction definitions.
The fixed-point Logical instructions from Book I,
extsw[.] and cntlzd[.] are available while executing in
VLE mode on 64-bit implementations. The mnemonics,
decoding, and semantics for these instructions are
identical to those in Book I; see Section 3.3.12 of Book
I for the instruction definitions.
AND (two operand) Immediate I16L-form AND (2 operand) Immediate Shifted
I16L-form
e_and2i. RT,ui
e_and2is. RT,ui
28 RT ui 25 ui
0 6 11 16 21 31 28 RT ui 29 ui
RT (RT) & ( 48 0 || ui)
The contents of register RT are ANDed with 48 0 || ui
and the result is placed into register RT.
Special Registers Altered:
CR0
0 6 11 16 21 31
RT (RT) & ( 32 0 || ui || 16 0)
The contents of register RT are ANDed with 32 0 || ui ||
16 0 and the result is placed into register RT.
Special Registers Altered:
CR0
AND Scaled Immediate Carrying
SCI8-form
e_andi RA,RS,sci8 (Rc=0)
e_andi. RA,RS,sci8 (Rc=1)
06 RS RA 12 Rc F SCL UI8
0 6 11 16 20 21 22 24 31
sci8 56-SCL×8 F || UI8 || SCL×8 F
RA (RS) & sci8
The contents of register RS are ANDed with sci8 and
the result is placed into register RA.
Special Registers Altered:
CR0
(if Rc=1)
AND Immediate Short Form
se_andi
RX,UI5
11 1 UI5 RX
0 6 7 12 15
RX (RX) & 59 0 || UI5
IM5-form
The contents of register RX are ANDed with 59 0 || UI5
and the result is placed into register RX.
Special Registers Altered:
None
680
Power ISA -- Book VLE