Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Shift Right Byte
VX-form
Vector Shift Right Halfword
VX-form
vsrb
VRT,VRA,VRB
vsrh
VRT,VRA,VRB
4 VRT VRA VRB 516
0 6 11 16 21 31
do i=0 to 127 by 8
sh (VRB) i+5:i+7
VRT i:i+7 (VRA) i:i+7 >> ui sh
For each vector element i from 0 to 15, do the following.
Byte element i in VRA is shifted right by the number
of bits specified in the low-order 3 bits of byte
element i in VRB. Bits shifted out of the least-significant
bit are lost. Zeros are supplied to the
vacated bits on the left. The result is placed into
byte element i of VRT.
Special Registers Altered:
None
4 VRT VRA VRB 580
0 6 11 16 21 31
do i=0 to 127 by 16
sh (VRB) i+12:i+15
VRT i:i+15 (VRA) i:i+15 >> ui sh
For each vector element i from 0 to 7, do the following.
Halfword element i in VRA is shifted right by the
number of bits specified in the low-order 4 bits of
halfword element i in VRB. Bits shifted out of the
least-significant bit are lost. Zeros are supplied to
the vacated bits on the left. The result is placed
into halfword element i of VRT.
Special Registers Altered:
None
Vector Shift Right Word
VX-form
vsrw
VRT,VRA,VRB
4 VRT VRA VRB 644
0 6 11 16 21 31
do i=0 to 127 by 32
sh (VRB) i+27:i+31
VRT i:i+31 (VRA) i:i+31 >> ui sh
For each vector element i from 0 to 3, do the following.
Word element i in VRA is shifted right by the number
of bits specified in the low-order 5 bits of word
element i in VRB. Bits shifted out of the least-significant
bit are lost. Zeros are supplied to the
vacated bits on the left. The result is placed into
word element i of VRT.
Special Registers Altered:
None
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Power ISA -- Book I