Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Multiply Odd Signed Byte VX-form Vector Multiply Odd Signed Halfword
VX-form
vmulosb VRT,VRA,VRB
vmulosh VRT,VRA,VRB
4 VRT VRA VRB 264
0 6 11 16 21 31 4 VRT VRA VRB 328
do i=0 to 127 by 16
prod EXTS((VRA) i+8:i+15 ) × si EXTS((VRB) i+8:i+15 )
VRT i:i+15 Chop( prod, 16 )
For each vector element i from 0 to 7, do the following.
Signed-integer byte element i×2+1 in VRA is multiplied
by signed-integer byte element i×2+1 in VRB.
The low-order 16 bits of the product are placed into
halfword element i VRT.
Special Registers Altered:
None
0 6 11 16 21 31
do i=0 to 127 by 32
prod EXTS((VRA) i+16:i+31 ) × si EXTS((VRB) i+16:i+31 )
VRT i:i+31 Chop( prod, 32 )
For each vector element i from 0 to 3, do the following.
Signed-integer halfword element i×2+1 in VRA is
multiplied by signed-integer halfword element
i×2+1 in VRB. The low-order 32 bits of the product
are placed into halfword element i VRT.
Special Registers Altered:
None
Vector Multiply Odd Unsigned Byte
VX-form
Vector Multiply Odd Unsigned Halfword
VX-form
vmuloub
VRT,VRA,VRB
vmulouh
VRT,VRA,VRB
4 VRT VRA VRB 8
0 6 11 16 21 31
do i=0 to 127 by 16
prod EXTZ((VRA) i+8:i+15 ) × ui EXTZ((VRB) i+8:i+15 )
VRT i:i+15 Chop( prod, 16 )
For each vector element i from 0 to 7, do the following.
Unsigned-integer byte element i×2+1 in VRA is
multiplied by unsigned-integer byte element i×2+1
in VRB. The low-order 16 bits of the product are
placed into halfword element i VRT.
Special Registers Altered:
None
4 VRT VRA VRB 72
0 6 11 16 21 31
do i=0 to 127 by 32
prod EXTZ((VRA) i+16:i+31 )× ui EXTZ((VRB) i+16:i+31 )
VRT i:i+31 Chop( prod, 32 )
For each vector element i from 0 to 3, do the following.
Unsigned-integer halfword element i×2+1 in VRA
is multiplied by unsigned-integer halfword element
i×2+1 in VRB. The low-order 32 bits of the product
are placed into halfword element i VRT.
Special Registers Altered:
None
162
Power ISA -- Book I