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Version 2.03
If the contents of the XER specifies a length of zero
bytes for a Move Assist instruction, a Data Storage
interrupt does not occur for reasons of address translation,
or storage protection. If such an instruction causes
a Data Storage interrupt for other reasons, the setting
of the DSISR and DAR reflects only these other reasons
listed in the preceding sentence. (E.g., if such an
instruction causes a storage protection violation and a
Data Address Breakpoint match, the DSISR and DAR
are set as if the storage protection violation did not
occur.)
The following registers are set:
SRR0 Set to the effective address of the instruction
that caused the interrupt.
SRR1
33:36 Set to 0.
42:47 Set to 0.
Others Loaded from the MSR.
MSR See Figure 34.
DSISR
32 Set to 0.
33 Set to 1 if MSR DR =1 and the translation for
an attempted access is not found in the primary
PTEG or in the secondary PTEG; otherwise
set to 0.
34:35 Set to 0.
36 Set to 1 if the access is not permitted by the
storage protection mechanism; otherwise
set to 0.
37 Set to 1 if the access is due to a lq, stq,
lwarx, ldarx, stwcx., or stdcx. instruction
that addresses storage that is Write
Through Required or Caching Inhibited;
otherwise set to 0.
38 Set to 1 for a Store, dcbz, or ecowx
instruction; otherwise set to 0.
39:40 Set to 0.
41 Set to 1 if a Data Address Compare match
or a Data Address Breakpoint match
occurs; otherwise set to 0.
42 Set to 0.
43 Set to 1 if execution of an eciwx or ecowx
instruction is attempted when EAR E =0; otherwise
set to 0.
44:63 Set to 0.
DAR
Set to the effective address of a storage
element as described in the following list.
The list should be read from the top down;
the DAR is set as described by the first item
that corresponds to an exception that is
reported in the DSISR. For example, if a
Load instruction causes a storage protection
violation and a Data Address Breakpoint
match (and both are reported in the
DSISR), the DAR is set to the effective
address of a byte in the first aligned doubleword
for which access was attempted in the
page that caused the exception.
a Data Storage exception occurs for
reasons other than a Data Address
Breakpoint match or, for eciwx and
ecowx, EAR E =0
- a byte in the block that caused the
exception, for a Cache Management
instruction
- a byte in the first aligned doubleword
for which access was
attempted in the page that caused
the exception, for a Load, Store,
eciwx, or ecowx instruction (“first”
refers to address order; see
Section 6.7)
undefined, for a Data Address Breakpoint
match, or if eciwx or ecowx is
executed when EAR E =0
For the cases in which the DAR is specified
above to be set to a defined value, if the
interrupt occurs in 32-bit mode the highorder
32 bits of the DAR are set to 0.
If multiple Data Storage exceptions occur for a given
effective address, any one or more of the bits corresponding
to these exceptions may be set to 1 in the
DSISR.
Programming Note
More than one bit may be set to 1 in the DSISR in
the following combinations.
33, {s+}
36, {s+}
36, 37, {s}
37, {s}
{s+}
In this list, “{s}” represents any combination of the
set of bits {38, 41} and “{s+}” adds bit 43 to this set.
Execution resumes at effective address
0x0000_0000_0000_0300.
6.5.4 Data Segment Interrupt
A Data Segment interrupt occurs when no higher priority
exception exists and a data access cannot be performed
because data address translation is enabled
and the effective address of any byte of the storage
location specified by a Load, Store, icbi, dcbz, dcbst,
dcbf[l] eciwx, or ecowx instruction cannot be translated
to a virtual address.
If a stwcx. or stdcx. would not perform its store in the
absence of a Data Segment interrupt, and a non-conditional
Store to the specified effective address would
cause a Data Segment interrupt, it is implementationdependent
whether a Data Segment interrupt occurs.
Chapter 6. Interrupts
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