Power ISA™ Version 2.03 - Power.org

Version 2.03
38 Interrupt Taken Debug Event Enable (IRPT)
0 IRPT debug events are disabled
1 IRPT debug events are enabled
Note: Critical interrupts will not cause an IRPT
Debug event even if MSR DE =0. If the Embedded.Enhanced
Debug category is supported,
see Section 8.4.9.
39 Trap Debug Event Enable (TRAP)
0 TRAP debug events cannot occur
1 TRAP debug events can occur
40 Instruction Address Compare 1 Debug
Event Enable (IAC1)
0 IAC1 debug events cannot occur
1 IAC1 debug events can occur
41 Instruction Address Compare 2 Debug
Event Enable (IAC2)
0 IAC2 debug events cannot occur
1 IAC2 debug events can occur
42 Instruction Address Compare 3 Debug
Event Enable (IAC3)
0 IAC3 debug events cannot occur
1 IAC3 debug events can occur
43 Instruction Address Compare 4 Debug
Event Enable (IAC4)
0 IAC4 debug events cannot occur
1 IAC4 debug events can occur
44:45 Data Address Compare 1 Debug Event
Enable (DAC1)
00 DAC1 debug events cannot occur
01 DAC1 debug events can occur only if a
store-type data storage access
10 DAC1 debug events can occur only if a
load-type data storage access
11 DAC1 debug events can occur on any
data storage access
46:47 Data Address Compare 2 Debug Event
Enable (DAC2)
00 DAC2 debug events cannot occur
01 DAC2 debug events can occur only if a
store-type data storage access
10 DAC2 debug events can occur only if a
load-type data storage access
11 DAC2 debug events can occur on any
data storage access
48 Return Debug Event Enable (RET)
0 RET debug events cannot occur
1 RET debug events can occur
Note: Return From Critical Interrupt will not
cause an RET debug event if MSR DE =0. If the
Embedded.Enhanced Debug category is supported,
see Section 8.4.10
49:56 Reserved
57 Critical Interrupt Taken Debug Event
(CIRPT)
[Category: Embedded.Enhanced Debug]
A Critical Interrupt Taken Debug Event occurs
when DBCR0 CIRPT = 1 and a critical interrupt
(any interrupt that uses the critical class, i.e.
uses CSRR0 and CSRR1) occurs.
0 Critical interrupt taken debug events are
disabled.
1 Critical interrupt taken debug events are
enabled.
58 Critical Interrupt Return Debug Event
(CRET)
[Category: Embedded.Enhanced Debug]
A Critical Interrupt Return Debug Event
occurs when DBCR0 CRET = 1 and a return
from critical interrupt (an rfci instruction is
executed) occurs.
0 Critical interrupt return debug events are
disabled.
1 Critical interrupt return debug events are
enabled.
59:62 Implementation-dependent
63 Freeze Timers on Debug Event (FT)
0 Enable clocking of timers
1 Disable clocking of timers if any DBSR bit
is set (except MRR)
8.5.1.2 Debug Control Register 1
(DCBR1)
The contents of the DCBR1 can be read into bits 32:63
a register RT using mfspr RT,DBCR1, setting bits 0:31
of RT to 0. The contents of bits 32:63 of register RS can
be written to the DBCR1 using mtspr DBCR1,RS. The
bit definitions for DCBR1 are shown below.
Bit(s) Description
32:33 Instruction Address Compare 1 User/
Supervisor Mode(IAC1US)
00 IAC1 debug events can occur
01 Reserved
10 IAC1 debug events can occur only if
MSR PR =0
11 IAC1 debug events can occur only if
MSR PR =1
592
Power ISA -- Book III-E