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Version 2.03
5.8.2 Vector Merge Instructions
Vector Merge High Byte
VX-form
Vector Merge High Halfword
VX-form
vmrghb
VRT,VRA,VRB
vmrghh
VRT,VRA,VRB
4 VRT VRA VRB 12
0 6 11 16 21 31
do i=0 to 63 by 8
VRT i×2:i×2+7 (VRA) i:i+7
VRT i×2+8:i×2+15 (VRB) i:i+7
For each vector element i from 0 to 7, do the following.
Byte element i in VRA is placed into byte element
2×i in VRT.
Byte element i in VRB is placed into byte element
2×i+1 in VRT.
Special Registers Altered:
None
4 VRT VRA VRB 76
0 6 11 16 21 31
do i=0 to 63 by 16
VRT i×2:i×2+15 (VRA) i:i+15
VRT i×2+16:i×2+31 (VRB) i:i+15
For each vector element i from 0 to 3, do the following.
Halfword element i in VRA is placed into halfword
element 2×i in VRT.
Halfword element i in VRB is placed into halfword
element 2×i+1 in VRT.
Special Registers Altered:
None
Vector Merge High Word
VX-form
vmrghw
VRT,VRA,VRB
4 VRT VRA VRB 140
0 6 11 16 21 31
do i=0 to 63 by 32
VRT i×2:i×2+31 (VRA) i:i+31
VRT i×2+32:i×2+63 (VRB) i:i+31
For each vector element i from 0 to 1, do the following.
Word element i in VRA is placed into word element
2×i in VRT.
Word element i in VRB is placed into word element
2×i+1 in VRT.
The word elements in the high-order half of VRA are
placed, in the same order, into the even-numbered
word elements of VRT. The word elements in the
high-order half of VRB are placed, in the same order,
into the odd-numbered word elements of VRT.
Special Registers Altered:
None
Chapter 5. Vector Processor [Category: Vector]
149