Power ISA™ Version 2.03 - Power.org

Version 2.03
MSR
CM MSR CM is set to MSR ICM .
CE, ME,
DE, ICM Unchanged.
All other defined MSR bits set to 0.
Instruction execution resumes at address IVPR 0:47 ||
IVOR9 48:59 ||0b0000.
5.6.11 Decrementer Interrupt
A Decrementer interrupt occurs when no higher priority
exception exists (see Section 5.9 on page 569), a Decrementer
exception exists (TSR DIS =1), and the interrupt
is enabled (TCR DIE =1 and MSR EE =1). See
Section 7.3 on page 577.
Programming Note
MSR EE also enables the External Input and Fixed-
Interval Timer interrupts.
SRR0, SRR1, MSR, and TSR are updated as follows:
SRR0 Set to the effective address of the next
instruction to be executed.
SRR1 Set to the contents of the MSR at the time
of the interrupt.
MSR
CM MSR CM is set to MSR ICM .
CE, ME,
DE, ICM Unchanged.
All other defined MSR bits set to 0.
TSR (See Section 7.5.1 on page 579.)
DIS Set to 1.
Instruction execution resumes at address IVPR 0:47 ||
IVOR10 48:59 ||0b0000.
Programming Note
Software is responsible for clearing the Decrementer
exception status prior to re-enabling the
MSR EE bit in order to avoid another redundant
Decrementer interrupt. To clear the Decrementer
exception, the interrupt handling routine must clear
TSR DIS . Clearing is done by writing a word to TSR
using mtspr with a 1 in any bit position that is to be
cleared and 0 in all other bit positions. The writedata
to the TSR is not direct data, but a mask. A 1
causes the bit to be cleared, and a 0 has no effect.
5.6.12 Fixed-Interval Timer Interrupt
A Fixed-Interval Timer interrupt occurs when no higher
priority exception exists (see Section 5.9 on page 569),
a Fixed-Interval Timer exception exists (TSR FIS =1),
and the interrupt is enabled (TCR FIE =1 and MSR EE =1).
See Section 7.6 on page 580.
Programming Note
MSR EE also enables the External Input and Decrementer
interrupts.
SRR0, SRR1, MSR, and TSR are updated as follows:
SRR0 Set to the effective address of the next
instruction to be executed.
SRR1 Set to the contents of the MSR at the time
of the interrupt.
MSR
CM MSR CM is set to MSR ICM .
CE, ME,
DE, ICM Unchanged.
All other defined MSR bits set to 0.
TSR (See Section 7.5.1 on page 579.)
FIS Set to 1
Instruction execution resumes at address IVPR 0:47 ||
IVOR11 48:59 ||0b0000.
Programming Note
Software is responsible for clearing the Fixed-Interval
Timer exception status prior to re-enabling the
MSR EE bit in order to avoid another redundant
Fixed-Interval Timer interrupt. To clear the Fixed-
Interval Timer exception, the interrupt handling routine
must clear TSR FIS . Clearing is done by writing
a word to TSR using mtspr with a 1 in any bit position
that is to be cleared and 0 in all other bit positions.
The write-data to the TSR is not direct data,
but a mask. A 1 causes the bit to be cleared, and a
0 has no effect.
5.6.13 Watchdog Timer Interrupt
A Watchdog Timer interrupt occurs when no higher priority
exception exists (see Section 5.9 on page 569), a
Watchdog Timer exception exists (TSR WIS =1), and the
interrupt is enabled (i.e. TCR WIE =1 and MSR CE =1).
See Section 7.7 on page 580.
Programming Note
MSR CE also enables the Critical Input interrupt.
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Power ISA -- Book III-E