Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Multiply Word Low Signed,
Modulo, Integer and Accumulate into
Words
EVX-form
evmwlsmiaaw RT,RA,RB
4 RT RA RB 1353
0 6 11 16 21 31
Vector Multiply Word Low Signed,
Modulo, Integer and Accumulate Negative
in Words
EVX-form
evmwlsmianw RT,RA,RB
4 RT RA RB 1481
0 6 11 16 21 31
temp 0:63 (RA) 0:31 × si (RB) 0:31
RT 0:31 (ACC) 0:31 + temp 32:63
temp 0:63 (RA) 32:63 × si (RB) 32:63
RT 32:63 (ACC) 32:63 + temp 32:63
ACC 0:63 (RT) 0:63
For each word element in the accumulator, the corresponding
word signed-integer elements in RA and RB
are multiplied. The least significant 32 bits of each
intermediate product are added to the contents of the
corresponding accumulator words, and the result is
placed in RT and the accumulator.
Special Registers Altered:
ACC
temp 0:63 (RA) 0:31 × si (RB) 0:31
RT 0:31 (ACC) 0:31 - temp 32:63
temp 0:63 (RA) 32:63 × si (RB) 32:63
RT 32:63 (ACC) 32:63 - temp 32:63
ACC 0:63 (RT) 0:63
For each word element in the accumulator, the corresponding
word elements in RA and RB are multiplied.
The least significant 32 bits of each intermediate product
are subtracted from the contents of the corresponding
accumulator words and the result is placed in RT
and the accumulator.
Special Registers Altered:
ACC
Vector Multiply Word Low Signed,
Saturate, Integer and Accumulate into
Words
EVX-form
evmwlssiaaw RT,RA,RB
4 RT RA RB 1345
0 6 11 16 21 31
Vector Multiply Word Low Signed,
Saturate, Integer and Accumulate
Negative in Words
EVX-form
evmwlssianw RT,RA,RB
4 RT RA RB 1473
0 6 11 16 21 31
temp 0:63 (RA) 0:31 × si (RB) 0:31
temp 0:63 EXTS((ACC) 0:31 ) + EXTS(temp 32:63 )
ovh (temp 31 ⊕ temp 32 )
RT 0:31 SATURATE(ovh, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
temp 0:63 (RA) 32:63 × si (RB) 32:63
temp 0:63 EXTS((ACC) 32:63 ) + EXTS(temp 32:63 )
ovl (temp 31 ⊕ temp 32 )
RT 32:63 SATURATE(ovl, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh
SPEFSCR OV ovl
SPEFSCR SOVH SPEFSCR SOVH | ovh
SPEFSCR SOV SPEFSCR SOV | ovl
The corresponding word signed-integer elements in RA
and RB are multiplied producing a 64-bit product. The
least significant 32 bits of each product are then added
to the corresponding word in the accumulator saturating
if overflow occurs, and the result is placed in RT
and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
temp 0:63 (RA) 0:31 × si (RB) 0:31
temp 0:63 EXTS((ACC) 0:31 ) - EXTS(temp 32:63 )
ovh (temp 31 ⊕ temp 32 )
RT 0:31 SATURATE(ovh, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
temp 0:63 (RA) 32:63 × si (RB) 32:63
temp 0:63 EXTS((ACC) 32:63 ) - EXTS(temp 32:63 )
ovl (temp 31 ⊕ temp 32 )
RT 32:63 SATURATE(ovl, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh
SPEFSCR OV ovl
SPEFSCR SOVH SPEFSCR SOVH | ovh
SPEFSCR SOV SPEFSCR SOV | ovl
The corresponding word signed-integer elements in RA
and RB are multiplied producing a 64-bit product. The
least significant 32 bits of each product are then subtracted
from the corresponding word in the accumulator
saturating if overflow occurs, and the result is placed in
RT and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
Chapter 6. Signal Processing Engine (SPE)
233