Power ISA™ Version 2.03 - Power.org

Version 2.03
TLB Invalidate Entry Local
tlbiel RB,L
[Category: Server]
X-form
if L = 0
then
p = 12
if (RB) 56 =0
then pg_size 4 KB
else pg_size 64 KB
else
pg_size page size specified in (RB) 44:51
p log_base_2(pg_size)
sg_size segment size specified in (RB) 54:55
for each TLB entry
if (entry_VA 14:77-p = (RB) 0:63-p ) &
(entry_sg_size = segment_size)
(entry_pg_size = pg_size)
then TLB entry invalid
The operation performed by this instruction is based
upon the contents of RB and the L field. The contents
of RB are shown below, where L is the L field in the
instruction.
L=0:
L=1:
31 /// L /// RB 274 /
0 6 10 11 16 21 31
VPN 0s B AP 0s
0 52 54 56 57 63
VPN LP 0s B 0s
0 44 52 54 56 63
If the L field of the instruction contains 0, RB 56 (AP -
Admixed Page size field) must be set to 0 if the page
size specified by the PTE that was used to create the
TLB entry to be invalidated is 4 KB and must be set to 1
if the page size specified by the PTE that was used to
create the TLB entry to be invalidated is 64 KB. The
VPN field in register RB must contain bits 14:65 of the
virtual address translated by the TLB entry to be invalidated.
If the L field in the instruction contains 1, the following
rules apply, where c is the number of “r” bits in the LP
field of the PTE that was used to create the TLB entry
to be invalidated.
- The page size is specified in the LP field in
register RB, where the relationship between
(RB) LP and the page size is the same as the
relationship between PTE LP and the page size
(see Figure 6). Specifically, (RB) 44+c:51
must be equal to the contents of bits c:7 of the
LP field of the PTE that was used to create the
TLB entry to be invalidated.
- (RB) 0:43+c must contain bits 14:77-p of the virtual
address translated by the TLB to be invalidated,
followed by p+c-20 zeros which must
be ignored by the processor.
Let the segment size be equal to the segment size
specified in RB 54:55 (B field). The contents of RB 54:55
must be the same as the contents of PTE B used to create
the TLB entry to be invalidated.
RB 52:53 , RB 56 (when the L field of the instruction is 1),
and RB 57:63 must be set to 0s and must be ignored by
the processor.
All TLB entries that have all of the following properties
are made invalid on the processor executing the tlbiel
instruction.
The entry translates a virtual address for which
VA 14:77-p is equal to (RB) 0:63-p .
The segment size of the entry is the same as the
segment size specified in (RB) 54:55
The L field in the instruction is 0, and either the
page size of the entry is 4KB and (RB) 56 =0 or the
page size of the entry is 64KB and (RB) 56 =1
The L field of the instruction is 1 and the page size
of the entry matches the page size specified in
(RB) 44:51 .
Only TLB entries on the processor executing the tlbiel
instruction are affected.
MSR SF must be 1 when this instruction is executed;
otherwise the results are undefined.
This instruction is privileged, and can be executed only
in hypervisor state. If it is executed in privileged but
non-hypervisor state either a Privileged Instruction type
Program interrupt occurs or the results are boundedly
undefined.
See Section 5.10, “Page Table Update Synchronization
Requirements” on page 436 for a description of other
requirements associated with the use of this instruction.
Special Registers Altered:
None
Programming Note
The primary use of this instruction by hypervisor
state code is to invalidate TLB entries prior to reassigning
a processor to a new logical partition.
tlbiel may be executed on a given processor even
if the sequence tlbie - eieio - tlbsync - ptesync is
concurrently being executed on another processor.
See also the Programming Note with the description
of the tlbie instruction.
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Power ISA -- Book III-S