Power ISA™ Version 2.03 - Power.org

Version 2.03
IEEE-conforming significand arithmetic is considered to
be performed with a floating-point accumulator having
the following format, where bits 0:55 comprise the significand
of the intermediate result.
S C L FRACTION G R X
0 1 53 54 55
Figure 51. IEEE 64-bit execution model
The S bit is the sign bit.
The C bit is the carry bit, which captures the carry out
of the significand.
The L bit is the leading unit bit of the significand, which
receives the implicit bit from the operand.
The FRACTION is a 52-bit field that accepts the fraction
of the operand.
The Guard (G), Round (R), and Sticky (X) bits are
extensions to the low-order bits of the accumulator. The
G and R bits are required for postnormalization of the
result. The G, R, and X bits are required during rounding
to determine if the intermediate result is equally
near the two nearest representable values. The X bit
serves as an extension to the G and R bits by representing
the logical OR of all bits that may appear to the
low-order side of the R bit, due either to shifting the
accumulator right or to other generation of low-order
result bits. The G and R bits participate in the left shifts
with zeros being shifted into the R bit. Figure 52 shows
the significance of the G, R, and X bits with respect to
the intermediate result (IR), the representable number
next lower in magnitude (NL), and the representable
number next higher in magnitude (NH).
G R X Interpretation
0 0 0 IR is exact
0 0 1
0 1 0 IR closer to NL
0 1 1
1 0 0 IR midway between NL and NH
1 0 1
1 1 0 IR closer to NH
1 1 1
Figure 52. Interpretation of G, R, and X bits
Figure 53 shows the positions of the Guard, Round,
and Sticky bits for double-precision and single-precision
floating-point numbers relative to the accumulator
illustrated in Figure 51.
The significand of the intermediate result is prepared
for rounding by shifting its contents right, if required,
until the least significant bit to be retained is in the
low-order bit position of the fraction. Four user-selectable
rounding modes are provided through FPSCR RN
as described in Section 4.3.6, “Rounding” on page 97.
Using Z1 and Z2 as defined on page 97, the rules for
rounding in each mode are as follows.
Round to Nearest
Guard bit = 0
The result is truncated. (Result exact (GRX=000)
or closest to next lower value in magnitude
(GRX=001, 010, or 011))
Guard bit = 1
Depends on Round and Sticky bits:
Case a
If the Round or Sticky bit is 1 (inclusive), the
result is incremented. (Result closest to
next higher value in magnitude (GRX=101,
110, or 111))
Case b
If the Round and Sticky bits are 0 (result
midway between closest representable values),
then if the low-order bit of the result is
1 the result is incremented. Otherwise (the
low-order bit of the result is 0) the result is
truncated (this is the case of a tie rounded
to even).
Round toward Zero
Choose the smaller in magnitude of Z1 or Z2. If the
Guard, Round, or Sticky bit is nonzero, the result is
inexact.
Round toward + Infinity
Choose Z1.
Round toward - Infinity
Choose Z2.
If rounding results in a carry into C, the significand is
shifted right one position and the exponent is incremented
by one. This yields an inexact result, and possibly
also exponent overflow. If any of the Guard, Round,
or Sticky bits is nonzero, then the result is also inexact.
Fraction bits are stored to the target FPR. For Floating
Round to Integer, Floating Round to Single-Precision,
and single-precision arithmetic instructions, low-order
zeros must be appended as appropriate to fill out the
double-precision fraction.
Format Guard Round Sticky
Double G bit R bit X bit
Single 24 25 OR of 26:52, G, R, X
Figure 53. Location of the Guard, Round, and
Sticky bits in the IEEE execution model
104
Power ISA -- Book I