Power ISA™ Version 2.03 - Power.org

Version 2.03
Divide Word XO-form
divw RT,RA,RB (OE=0 Rc=0)
divw. RT,RA,RB (OE=0 Rc=1)
divwo RT,RA,RB (OE=1 Rc=0)
divwo. RT,RA,RB (OE=1 Rc=1)
31 RT RA RB OE 491 Rc
0 6 11 16 21 22 31
Divide Word Unsigned XO-form
divwu RT,RA,RB (OE=0 Rc=0)
divwu. RT,RA,RB (OE=0 Rc=1)
divwuo RT,RA,RB (OE=1 Rc=0)
divwuo. RT,RA,RB (OE=1 Rc=1)
31 RT RA RB OE 459 Rc
0 6 11 16 21 22 31
dividend 0:63 EXTS((RA) 32:63 )
divisor 0:63 EXTS((RB) 32:63 )
RT 32:63 dividend ÷ divisor
RT 0:31 undefined
The 64-bit dividend is the sign-extended value of
(RA) 32:63 . The 64-bit divisor is the sign-extended value
of (RB) 32:63 . The 64-bit quotient is formed. The
low-order 32 bits of the 64-bit quotient are placed into
RT 32:63 . The contents of RT 0:31 are undefined. The
remainder is not supplied as a result.
Both operands and the quotient are interpreted as
signed integers. The quotient is the unique signed integer
that satisfies
dividend = (quotient × divisor) + r
where 0 ≤ r < |divisor| if the dividend is nonnegative,
and -|divisor| < r ≤ 0 if the dividend is negative.
If an attempt is made to perform any of the divisions
0x8000_0000 ÷ -1
÷ 0
then the contents of register RT are undefined as are
(if Rc=1) the contents of the LT, GT, and EQ bits of CR
Field 0. In these cases, if OE=1 then OV is set to 1.
Special Registers Altered:
CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
SO OV
(if OE=1)
Programming Note
The 32-bit signed remainder of dividing (RA) 32:63
by (RB) 32:63 can be computed as follows, except in
the case that (RA) 32:63 = -2 31 and (RB) 32:63 = -1.
divw RT,RA,RB # RT = quotient
mullw RT,RT,RB # RT = quotient×divisor
subf RT,RT,RA # RT = remainder
dividend 0:63 32 0 || (RA) 32:63
divisor 0:63 32 0 || (RB) 32:63
RT 32:63 dividend ÷ divisor
RT 0:31 undefined
The 64-bit dividend is the zero-extended value of
(RA) 32:63 . The 64-bit divisor is the zero-extended value
of (RB) 32:63 . The 64-bit quotient is formed. The
low-order 32 bits of the 64-bit quotient are placed into
RT 32:63 . The contents of RT 0:31 are undefined. The
remainder is not supplied as a result.
Both operands and the quotient are interpreted as
unsigned integers, except that if Rc=1 the first three
bits of CR Field 0 are set by signed comparison of the
result to zero. The quotient is the unique unsigned
integer that satisfies
dividend = (quotient × divisor) + r
where 0 ≤ r < divisor.
If an attempt is made to perform the division
÷ 0
then the contents of register RT are undefined as are (if
Rc=1) the contents of the LT, GT, and EQ bits of CR
Field 0. In this case, if OE=1 then OV is set to 1.
Special Registers Altered:
CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
SO OV
(if OE=1)
Programming Note
The 32-bit unsigned remainder of dividing (RA) 32:63
by (RB) 32:63 can be computed as follows.
divwu RT,RA,RB # RT = quotient
mullw RT,RT,RB # RT = quotient×divisor
subf RT,RT,RA # RT = remainder
Chapter 3. Fixed-Point Processor
61