Power ISA™ Version 2.03 - Power.org

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Version 2.03 Table 6: (Left) Extended opcodes for primary opcode 4 [Category: SP.*] (instruction bits 21:31) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 00000 00001 00010 00011 00100 00101 00110 00111 01000 512 evaddw SP EVX 514 evaddiw SP EVX 516 evsubfw SP EVX 518 evsubifw SP EVX 520 evabs SP EVX 521 evneg SP EVX 522 evextsb SP EVX 523 evextsh SP EVX 524 evrndw SP EVX 525 evcntlzw SP EVX 526 evcntlsw SP EVX 527 brinc SP EVX 01001 640 641 01010 evfsadd evssub sp.fv EVX sp.fv EVX 704 705 01011 efsadd efssub sp.fs EVX sp.fs EVX 769 01100 01101 768 evlddx SP EVX evldd SP EVX 770 evldwx SP EVX 771 evldw SP EVX 644 evfsabs sp.fv EVX 708 efsabs sp.fs EVX 772 evldhx SP EVX 645 evfsnabs sp.fv EVX 709 efsnabs sp.fs EVX 773 evldh SP EVX 646 evfsneg sp.fv EVX 710 efsneg sp.fs EVX 648 evfsmul sp.fv EVX 712 efsmul 649 evfsdiv sp.fv EVX 713 efsdiv sp.fs EVX sp.fs EVX 776 long SP EVX 777 long SP EVX 652 653 654 long evfscmplt long sp.fv EVX sp.fv EVX sp.fv EVX 716 717 718 719 efscmpgt efscmplt efscmpeq efscfd sp.fs EVX sp.fs EVX sp.fs EVX sp.fd EVX 780 781 782 783 long long long long SP EVX SP EVX SP EVX SP EVX 01110 01111 10000 10001 1027 evmhessf SP EVX 1031 1032 1033 evmhossf long long SP EVX SP EVX SP EVX 1095 1096 long long SP EVX SP EVX 1035 long SP EVX 1036 long SP EVX 1037 long SP EVX 1100 1101 long long SP EVX SP EVX 1039 long SP EVX 1103 long SP EVX 10010 1216 1217 10011 long long SP EVX SP EVX 1280 1281 10100 long long SP EVX SP EVX 1344 1345 10101 long long SP EVX SP EVX 1408 1409 10110 long long SP EVX SP EVX 1472 1473 10111 long long SP EVX SP EVX 1218 long SP EVX 1219 long SP EVX 1283 long SP EVX 1411 long SP EVX 1220 evmra SP EVX 1412 long SP EVX 1285 long SP EVX 1413 long SP EVX 1222 evdivws SP EVX 1223 evdivwu SP EVX 1287 long SP EVX 1415 long SP EVX 1224 long SP EVX 1288 long SP EVX 1352 long SP EVX 1416 long SP EVX 1480 long SP EVX 1225 long SP EVX 1289 long SP EVX 1353 long SP EVX 1417 long SP EVX 1481 long SP EVX 1226 long SP EVX 1227 long SP EVX 1291 long SP EVX 1419 long SP EVX 1292 long SP EVX 1420 long SP EVX 1293 long SP EVX 1421 long SP EVX 1295 long SP EVX 1423 long SP EVX 11000 11001 11010 11011 11100 11101 11110 11111 752 Power ISA -- Book Appendices
Version 2.03 Table 6 (Left-Center) Extended opcodes for primary opcode 4 [Category: SP.*] (instruction bits 21:31) 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 00000 00001 00010 00011 00100 00101 00110 00111 01000 529 530 evand evandc SP EVX SP EVX 534 evxor SP EVX 535 evor SP EVX 536 evnor SP EVX 537 eveqv SP EVX 539 evorc SP EVX 542 evnand SP EVX 01001 656 657 658 659 660 661 662 663 664 01010 evfsfui evfscfsi evfscfuf evfscfsf evfsctui evfsctsi evfsctuf evfsctsf evfsctuiz sp.fv EVX sp.fv EVX sp.fv EVX sp.fv EVX sp.fv EVX sp.fv EVX sp.fv EVX sp.fv EVX sp.fv EVX 720 721 722 723 724 725 726 727 728 01011 efscfui efscfsi efscfuf efscfsf efsctui efsctsi efsctuf efsctsf efsctuiz sp.fs EVX sp.fs EVX sp.fs EVX sp.fs EVX sp.fs EVX sp.fs EVX sp.fs EVX sp.fs EVX sp.fs EVX 784 01100 evlwhex SP EVX 785 evlwhe SP EVX 788 evlwhoux SP EVX 789 evlwhou SP EVX 790 evlwhosx SP EVX 791 evlwhos SP EVX 792 long SP EVX 793 long SP EVX 666 evfsctsiz sp.fv EVX 730 efsctsiz sp.fs EVX 668 evfststgt sp.fv EVX 732 efststgt sp.fs EVX 796 long SP EVX 669 evfststlt sp.fv EVX 733 efststlt sp.fs EVX 797 long SP EVX 670 evfststeq sp.fv EVX 734 efststeq sp.fs EVX 01101 01110 01111 10000 10001 1112 1113 long long SP EVX SP EVX 1115 long SP EVX 10010 10011 10100 10101 1363 long SP EVX 1368 1369 long long SP EVX SP EVX 1371 long SP EVX 10110 10111 1491 long SP EVX 1496 1497 long long SP EVX SP EVX 1499 long SP EVX 11000 11001 11010 11011 11100 11101 11110 11111 753
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® Power ISA Version 2.03 September
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Version 2.03 Preface The roots of t
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Version 2.03 Table of Contents Pref
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Version 2.03 Chapter 5. Vector Proc
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Version 2.03 D.8 Move To/From Speci
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Version 2.03 5.7.1 32-Bit Mode . .
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Version 2.03 4.6 Invalid Real Addre
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Version 2.03 8.6 Debugger Notify Ha
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Version 2.03 5.8 Fixed-Point Select
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Version 2.03 Figures Preface ......
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Version 2.03 40. MMU Control and St
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Version 2.03 Book I: Power ISA User
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Version 2.03 Chapter 1. Introductio
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Version 2.03 GPR, FPR, or VR (e.g.
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Version 2.03 SPR(x) Special Purpose
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Version 2.03 An instruction in a ca
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Version 2.03 CR 32 63 “Condition
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Version 2.03 1.6.3 SC-FORM 0 6 11 1
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Version 2.03 1.6.19 EVX-FORM 0 6 11
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Version 2.03 SPR (11:20) Field used
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Version 2.03 for each virtual page,
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Version 2.03 beq done loop: cmplwi
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Version 2.03 Chapter 2. Branch Proc
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Version 2.03 or (RB) (unsigned comp
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Version 2.03 Programming Note Many
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Version 2.03 Branch I-form Branch C
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Version 2.03 2.5 Condition Register
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Version 2.03 2.6 System Call Instru
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Version 2.03 Chapter 3. Fixed-Point
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Version 2.03 3.2.3 Program Priority
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Version 2.03 Load Byte and Zero D-f
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Version 2.03 Load Halfword Algebrai
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Version 2.03 3.3.2.1 64-bit Fixed-P
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Version 2.03 3.3.3 Fixed-Point Stor
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Version 2.03 Store Word D-form Stor
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Version 2.03 3.3.4 Fixed-Point Load
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Version 2.03 3.3.6 Fixed-Point Move
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Version 2.03 Store String Word Imme
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Version 2.03 3.3.8 Fixed-Point Arit
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Version 2.03 Subtract From Immediat
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Version 2.03 Add to Zero Extended X
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Version 2.03 Divide Word XO-form di
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Version 2.03 Divide Doubleword XO-f
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Version 2.03 Compare Logical Immedi
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Version 2.03 3.3.10.1 64-bit Fixed-
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Version 2.03 OR Immediate Shifted D
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Version 2.03 NOR X-form Equivalent
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Version 2.03 3.3.12.1 64-bit Fixed-
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Version 2.03 Rotate Left Word Immed
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Version 2.03 3.3.13.1.1 64-bit Fixe
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Version 2.03 Rotate Left Doubleword
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Version 2.03 Shift Right Algebraic
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Version 2.03 3.3.14 Move To/From Sy
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Version 2.03 Move To Condition Regi
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Version 2.03 3.3.14.1 Move To/From
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Version 2.03 Chapter 4. Floating-Po
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Version 2.03 the FPRs with no conve
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Version 2.03 59 Floating-Point Zero
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Version 2.03 due to the invalid ope
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Version 2.03 Programming Note The F
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Version 2.03 When an exception occu
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Version 2.03 When Invalid Operation
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Version 2.03 4.4.5 Inexact Exceptio
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Version 2.03 4.5.2 Execution Model
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Version 2.03 Load Floating-Point Si
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Version 2.03 4.6.3 Floating-Point S
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Version 2.03 Store Floating-Point D
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Version 2.03 4.6.4 Floating-Point M
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Version 2.03 Floating Multiply [Sin
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Version 2.03 Floating Reciprocal Sq
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Version 2.03 Floating Negative Mult
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Version 2.03 Floating Convert To In
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Version 2.03 Floating Round to Inte
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Version 2.03 4.6.8 Floating-Point S
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Version 2.03 Move To FPSCR Bit 0 X-
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Version 2.03 Chapter 5. Vector Proc
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Version 2.03 Quadword Word 0 Word 1
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Version 2.03 halfword, or word resp
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Version 2.03 5.5 Vector Integer Ope
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Version 2.03 If an exception occurs
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Version 2.03 5.7.2 Vector Load Inst
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Version 2.03 5.7.3 Vector Store Ins
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Version 2.03 5.7.4 Vector Alignment
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Version 2.03 Vector Pack Signed Hal
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Version 2.03 Vector Unpack High Pix
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Version 2.03 5.8.2 Vector Merge Ins
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Version 2.03 5.8.3 Vector Splat Ins
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Version 2.03 5.8.6 Vector Shift Ins
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Version 2.03 5.9 Vector Integer Ins
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Version 2.03 Vector Add Unsigned By
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Version 2.03 Vector Subtract Unsign
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Version 2.03 5.9.1.3 Vector Integer
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Version 2.03 Vector Multiply-Sum Si
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Version 2.03 Vector Minimum Signed
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Version 2.03 5.9.2 Vector Integer C
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Version 2.03 Vector Compare Greater
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Version 2.03 5.9.4 Vector Integer R
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Version 2.03 Vector Shift Right Alg
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Version 2.03 5.10 Vector Floating-P
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Version 2.03 5.10.2 Vector Floating
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Version 2.03 Vector Convert from Si
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Version 2.03 5.11 Vector Status and
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Version 2.03 Chapter 6. Signal Proc
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Version 2.03 has occurred in the up
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Version 2.03 If the exception is en
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Version 2.03 6.3.7 SPE Instructions
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Version 2.03 Vector Add Signed, Sat
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Version 2.03 Vector Compare Greater
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Version 2.03 Vector Divide Word Uns
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Version 2.03 Vector Load Double int
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Version 2.03 Vector Load Word into
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Version 2.03 Vector Load Word into
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Version 2.03 Vector Multiply Halfwo
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Version 2.03 Initialize Accumulator
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Version 2.03 Vector Multiply Word L
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Version 2.03 Vector Multiply Word L
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Version 2.03 Vector Multiply Word S
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Version 2.03 Vector Multiply Word U
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Version 2.03 Vector Rotate Left Wor
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Version 2.03 Vector Shift Right Wor
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Version 2.03 Vector Store Word of T
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Version 2.03 Vector Subtract Unsign
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Version 2.03 Chapter 7. Embedded Fl
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Version 2.03 Denormalized numbers o
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Version 2.03 7.3 Embedded Floating-
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Version 2.03 Vector Floating-Point
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Version 2.03 Vector Floating-Point
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Version 2.03 Vector Convert Floatin
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Version 2.03 7.3.3 SPE.Embedded Flo
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Version 2.03 Floating-Point Single-
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Version 2.03 Floating-Point Single-
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Version 2.03 Convert Floating-Point
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Version 2.03 Floating-Point Double-
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Version 2.03 Floating-Point Double-
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Version 2.03 7.4 Embedded Floating-
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Version 2.03 Table 3: Embedded Floa
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Version 2.03 Table 7: Embedded Floa
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Version 2.03 Chapter 8. Legacy Move
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Version 2.03 Chapter 9. Legacy Inte
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Version 2.03 Multiply Accumulate Hi
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Version 2.03 Multiply Accumulate Lo
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Version 2.03 Multiply High Halfword
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Version 2.03 Negative Multiply Accu
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Version 2.03 Appendix A. Suggested
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Version 2.03 If FPSCR RN = 0b01 the
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Version 2.03 A.2 Floating-Point Con
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Version 2.03 Large Operand: FPSCR F
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Version 2.03 A.4 Floating-Point Rou
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Version 2.03 Appendix B. Vector RTL
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Version 2.03 Appendix C. Embedded F
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Version 2.03 C.3 Convert from Doubl
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Version 2.03 C.5 Convert to Single-
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Version 2.03 Appendix D. Assembler
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Version 2.03 D.2.3 Branch Mnemonics
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Version 2.03 D.4 Subtract Mnemonics
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Version 2.03 These codes are reflec
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Version 2.03 D.7.2 Operations on Wo
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Version 2.03 Load Address This mnem
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Version 2.03 Appendix E. Programmin
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Version 2.03 Multiple-precision shi
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Version 2.03 E.2.5 Conversion from
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Version 2.03 E.4 Vector Unaligned S
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Version 2.03 Book II: Power ISA Vir
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Version 2.03 Chapter 1. Storage Mod
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Version 2.03 Each program can acces
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Version 2.03 cause additional locat
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Version 2.03 1.7 Shared Storage Thi
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Version 2.03 Programming Note The f
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Version 2.03 Programming Note Becau
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Version 2.03 1.8.1 Concurrent Modif
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Version 2.03 Chapter 2. Effect of O
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Version 2.03 Chapter 3. Storage Con
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Version 2.03 3.2.2 Data Cache Instr
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Version 2.03 description assumes th
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Version 2.03 Programming Note This
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Version 2.03 Data Cache Block set t
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Version 2.03 3.2.2.1 Obsolete Data
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Version 2.03 Store Word Conditional
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Version 2.03 3.3.3 Memory Barrier I
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Version 2.03 Enforce In-order Execu
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Version 2.03 Chapter 4. Time Base 4
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Version 2.03 Programming Note Since
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Version 2.03 Chapter 5. External Co
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Version 2.03 Appendix A. Assembler
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Version 2.03 Appendix B. Programmin
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Version 2.03 B.2 Lock Acquisition a
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Version 2.03 B.3 List Insertion Thi
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Version 2.03 Book III-S: Power ISA
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Version 2.03 the execution of a Ve
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Version 2.03 Chapter 2. Logical Par
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Version 2.03 2.5 Logical Partition
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Version 2.03 3.3 Branch Processor I
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Version 2.03 4.3.5 Software-use SPR
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Version 2.03 4.4.2 OR Instruction o
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Version 2.03 Move To Special Purpos
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Version 2.03 Move To Machine State
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Version 2.03 stream being executed)
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Version 2.03 5.7.2.3 Storage Contro
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Version 2.03 5.7.5 Virtual Address
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Version 2.03 5.7.6 Virtual to Real
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Version 2.03 A virtual page is mapp
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Version 2.03 The 62-bit real addres
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Version 2.03 not necessarily perfor
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Version 2.03 5.8 Storage Control At
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Version 2.03 5.9 Storage Control In
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Version 2.03 information used in ad
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Version 2.03 SLB Move From Entry VS
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Version 2.03 Move To Segment Regist
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Version 2.03 5.9.3.3 TLB Management
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Version 2.03 TLB Invalidate All tlb
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Version 2.03 Programming Note The e
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Version 2.03 Chapter 6. Interrupts
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Version 2.03 6.3 Interrupt Synchron
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Version 2.03 Programming Note For i
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Version 2.03 6.5 Interrupt Definiti
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Version 2.03 If the contents of the
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Version 2.03 to fetch a branch targ
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Version 2.03 Programming Note These
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Version 2.03 Execution resumes at e
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Version 2.03 6.8 Interrupt Prioriti
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Version 2.03 Chapter 7. Timer Facil
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Version 2.03 “Assembler Extended
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Version 2.03 Chapter 8. Debug Facil
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Version 2.03 Programming Note Proce
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Version 2.03 Chapter 9. External Co
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Version 2.03 Chapter 10. Synchroniz
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Version 2.03 Notes: 1. The effect o
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Version 2.03 Appendix A. Assembler
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Version 2.03 Appendix B. Example Pe
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Version 2.03 reflected in Performan
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Version 2.03 Programming Note Time
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Version 2.03 32 Contents of SIAR an
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Version 2.03 Appendix C. Example Tr
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Version 2.03 Appendix D. Interpreta
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Version 2.03 Book III-E: Power ISA
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Version 2.03 1.6 Synchronization Th
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Version 2.03 2.3 Branch Processor I
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Version 2.03 Return From Machine-Ch
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Version 2.03 3.3.4 External Process
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Version 2.03 3.4 Fixed-Point Proces
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Version 2.03 Move To Special Purpos
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Version 2.03 Move From Device Contr
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Version 2.03 3.4.2 External Process
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Version 2.03 Store Byte by External
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Version 2.03 Data Cache Block Store
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Version 2.03 Data Cache Block Touch
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Version 2.03 Load Floating-Point Do
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Version 2.03 Load Vector by Externa
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Version 2.03 4.6 Invalid Real Addre
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Version 2.03 SX Supervisor State Ex
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Version 2.03 MSR DS for data storag
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Version 2.03 4.7.4 Storage Access C
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Version 2.03 Programming Note This
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Version 2.03 Accesses to the same s
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Version 2.03 4.9.2 Cache Locking [C
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Version 2.03 4.9.2.3 Cache Locking
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Version 2.03 4.9.3 Synchronize Inst
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Version 2.03 TLB Search Indexed X-f
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Version 2.03 Chapter 5. Interrupts
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Version 2.03 5.2.3 Critical Save/Re
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Version 2.03 5.2.9 Exception Syndro
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Version 2.03 5.2.11.1 Machine Check
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Version 2.03 exception that generat
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Version 2.03 Programming Note For i
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Version 2.03 IVOR Interrupt Excepti
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Version 2.03 5.6.3 Data Storage Int
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Version 2.03 cessing system. Also,
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Version 2.03 MSR CM MSR CM is set t
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Version 2.03 CSRR0, CSRR1, MSR, and
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Version 2.03 5.6.17 SPE/Embedded Fl
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Version 2.03 5.6.21 Processor Doorb
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Version 2.03 5.8 Interrupt Ordering
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Version 2.03 5.8.2 Interrupt Order
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Version 2.03 5.9.1.5 Exception Prio
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Version 2.03 Chapter 6. Reset and I
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Version 2.03 Chapter 7. Timer Facil
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Version 2.03 7.3 Decrementer The De
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Version 2.03 Bit(s) Description 32:
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Version 2.03 Time-out. No exception
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Version 2.03 Chapter 8. Debug Facil
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Version 2.03 Programming Note There
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Version 2.03 Later, if the debug ex
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Version 2.03 whose direction will b
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Version 2.03 8.4.10 Critical Interr
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Version 2.03 34:35 Instruction Addr
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Version 2.03 40:41 Data Address Com
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Version 2.03 8.5.3 Instruction Addr
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Version 2.03 Chapter 9. Processor C
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Version 2.03 9.3 Processor Control
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Version 2.03 Chapter 10. Synchroniz
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Version 2.03 If an mtmsr, wrtee, or
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Version 2.03 Appendix A. Implementa
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Version 2.03 A.2.1.3 Instruction Ca
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Version 2.03 Instruction Cache Read
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Version 2.03 Appendix B. Assembler
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Version 2.03 Appendix C. Guidelines
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Version 2.03 Appendix D. Type FSL S
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Version 2.03 52:63 Next Victim (NV)
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Version 2.03 58 Default VLE Value (
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Version 2.03 D.2.5 MMU Configuratio
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Version 2.03 D.4.3 Invalidating TLB
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Version 2.03 D.6 Type FSL MMU Instr
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Version 2.03 TLB Synchronize XL-for
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Version 2.03 Appendix E. Example Pe
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Version 2.03 counter with an event
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Version 2.03 111 Threshold field is
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Version 2.03 E.5 Performance Monito
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Version 2.03 Book VLE: Power ISA Op
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Version 2.03 Chapter 1. Variable Le
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Version 2.03 1.4.6 R-form (16-bit M
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Version 2.03 UI (6:10 || 21:31, 11:
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Version 2.03 Chapter 2. VLE Storage
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Version 2.03 ESR MIF is set when an
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Version 2.03 Chapter 3. VLE Compati
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Version 2.03 Chapter 4. Branch Oper
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Version 2.03 4.2 Branch Instruction
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Version 2.03 Branch to Count Regist
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Version 2.03 Return From Machine Ch
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Version 2.03 4.4 Condition Register
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Version 2.03 Load Halfword Algebrai
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Version 2.03 5.2 Fixed-Point Store
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Version 2.03 Store Word D-form Stor
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Version 2.03 5.5 Fixed-Point Arithm
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Version 2.03 Add Scaled Immediate C
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Version 2.03 5.6 Fixed-Point Compar
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Version 2.03 Compare Logical Scaled
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Version 2.03 Compare Halfword Logic
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Version 2.03 OR (two operand) Immed
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Version 2.03 Extend Sign Byte Short
Page 707 and 708:
Version 2.03 5.10 Fixed-Point Rotat
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Version 2.03 Shift Right Algebraic
Page 711 and 712:
Page 713 and 714:
Version 2.03 Chapter 7. Additional
Page 715 and 716:
Version 2.03 Appendix A. VLE Instru
Page 717 and 718:
Version 2.03 Form Mode Dep. 1 Priv
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Page 721 and 722:
Page 723 and 724: Version 2.03 Form Mode Dep. 1 Priv
Page 731 and 732: Version 2.03 Appendix B. VLE Instru
Page 747 and 748: Version 2.03 Appendices: Power ISA
Page 749 and 750: Version 2.03 Appendix A. Incompatib
Page 751 and 752: Version 2.03 In POWER bits 20:26
Page 753 and 754: Version 2.03 privilege: mfsr and mf
Page 755 and 756: Version 2.03 A.32 POWER2 Compatibil
Page 757 and 758: Version 2.03 Appendix B. Platform S
Page 759 and 760: Version 2.03 Appendix C. Complete S
Page 761 and 762: Version 2.03 decimal SPR 1 Register
Page 763 and 764: Version 2.03 Appendix D. Illegal In
Page 765 and 766: Version 2.03 Appendix E. Reserved I
Page 767 and 768: Version 2.03 Appendix F. Opcode Map
Page 769 and 770: Version 2.03 Table 2: Extended opco
Page 771 and 772: Version 2.03 Table 5 (Left-Center)
Page 773: Version 2.03 Table 5 (Right) Extend
Page 777 and 778: Version 2.03 Table 6 (Right) Extend
Page 779 and 780: Version 2.03 Table 7. (Right) Exten
Page 781 and 782: Version 2.03 Table 8. (Right) Exten
Page 783 and 784: Version 2.03 761
Page 785 and 786: Version 2.03 763 Table 13. (Right)
Page 787 and 788: Version 2.03 765 Table 14. (Right)
Page 789 and 790: Version 2.03 Appendix G. Power ISA
Page 791 and 792: Version 2.03 Form Opcode Pri Ext Mo
Page 805 and 806: Version 2.03 Appendix H. Power ISA
Page 821 and 822: Version 2.03 Appendix I. Power ISA
Page 825 and 826:
Version 2.03 Form Opcode Pri Ext Mo
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Page 837 and 838:
Version 2.03 Mode Dependency and Pr
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Version 2.03 Index A a bit 26 A-for
Page 841 and 842:
Version 2.03 F FE 25, 92 FEX 91 FE0
Page 843 and 844:
Version 2.03 instructions classes 1
Page 845 and 846:
Version 2.03 Machine Status Save Re
Page 847 and 848:
Version 2.03 See Logical Partitioni
Page 849 and 850:
Version 2.03 Last Page - End of Doc
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