Power ISA™ Version 2.03 - Power.org

Version 2.03
Store Byte by External Process ID
Indexed
X-form
Store Halfword by External Process ID
Indexed
X-form
stbepx
RS,RA,RB
sthepx
RS,RA,RB
31 RS RA RB 223 /
0 6 11 16 21 31
if RA = 0 then b 0
else
b (RA)
EA b + (RB)
MEM(EA,1) (RS) 56:63
Let the effective address (EA) be the sum (RA|0)+(RB).
(RS) 56:63 are stored into the byte in storage addressed
by EA.
For stbepx, the normal translation mechanism is not
used. The contents of the EPSC register are used to
provide the context in which translation occurs. The following
substitutions are made for just the translation
and access control process:
EPSC EPR is used in place of MSR PR
EPSC EAS is used in place of MSR DS
EPSC EPID is used in place of all Process ID registers.
This instruction is privileged.
Special Registers Altered:
None
Programming Note
This instruction behaves identically to a stbx
instruction except for using the EPSC register to
provide the translation context.
31 RS RA RB 415 /
0 6 11 16 21 31
if RA = 0 then b 0
else
b (RA)
EA b + (RB)
MEM(EA,2) (RS) 48:63
Let the effective address (EA) be the sum (RA|0)+(RB).
(RS) 48:63 are stored into the halfword in storage
addressed by EA.
For sthepx, the normal translation mechanism is not
used. The contents of the EPSC register are used to
provide the context in which translation occurs. The following
substitutions are made for just the translation
and access control process:
EPSC EPR is used in place of MSR PR
EPSC EAS is used in place of MSR DS
EPSC EPID is used in place of all Process ID registers.
This instruction is privileged.
Special Registers Altered:
None
Programming Note
This instruction behaves identically to a sthx
instruction except for using the EPSC register to
provide the translation context.
Chapter 3. Fixed-Point Processor
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