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IVOR Interrupt Exception
IVOR15 Debug Trap x x DE IDM E 10 562
Inst Addr Compare x x DE IDM E 10
Data Addr Compare x x DE IDM E 10
Instruction Complete x x DE IDM E 3,10
Branch Taken x x DE IDM E 3,10
Return From Interrupt x x DE IDM E 10
Interrupt Taken x x DE IDM E 10
Uncond Debug Event x x
DE IDM E.ED 10
Critical Interrupt Taken x
DE IDM E.ED
Critical Interrupt Return x
DE IDM E.ED
IVOR32 SPE/Embedded SPE Unavailable x SPV, [VLEMI] SPE 563
Floating-Point/Vector
Unavailable
Vector Unavailable SPV V
IVOR33 Embedded Floating- Embedded Floating-Point x SPV, [VLEMI] SP.F* 563
Point Data
Data
IVOR34 Embedded Floating- Embedded Floating-Point x SPV, [VLEMI] SP.F* 564
Point Round Round
IVOR35 Embedded Performance
Embedded Performance x
E.PM
Monitor Monitor
IVOR36 Processor Doorbell Processor Doorbell x EE E.PC
IVOR37 Processor Critical
Doorbell
Processor Critical Doorbell x x CE E.PC
Figure 15. Interrupt and Exception Types
Asynchronous
Synchronous, Precise
Synchronous, Imprecise
Critical
ESR
(See Note 5)
MSR Mask Bit(s)
DBCR0/TCR Mask Bit
Category
(Section 1.3.5 of Book I)
Notes (see page 553)
Page
Figure 15 Notes
1. Although it is not specified, it is common for system
implementations to provide, as part of the
interrupt controller, independent mask and status
bits for the various sources of Critical Input and
External Input interrupts.
2. Machine Check interrupts are a special case and
are not classified as asynchronous nor synchronous.
See Section 5.4.4 on page 549.
3. The Instruction Complete and Branch Taken
debug events are only defined for MSR DE =1 when
in Internal Debug Mode (DBCR0 IDM =1). In other
words, when in Internal Debug Mode with
MSR DE =0, then Instruction Complete and Branch
Taken debug events cannot occur, and no DBSR
status bits are set and no subsequent imprecise
Debug interrupt will occur (see Section 8.4 on
page 584).
4. Machine Check status information is commonly
provided as part of the system implementation, but
is implementation-dependent.
5. In general, when an interrupt causes a particular
ESR bit or bits to be set (or cleared) as indicated in
the table, it also causes all other ESR bits to be
cleared. There may be special rules regarding the
handling of implementation-specific ESR bits.
Legend:
[xxx] means ESR xxx could be set
[xxx,yyy] means either ESR xxx or ESR yyy
may be set, but never both
(xxx,yyy) means either ESR xxx or ESR yyy
will be set, but never both
{xxx,yyy} means either ESR xxx or ESR yyy will
be set, or possibly both
xxx means ESR xxx is set
Chapter 5. Interrupts and Exceptions
553