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Appendix E. Example Performance Monitor
[Category: Embedded.Performance Monitor]
E.1 Overview
This appendix describes an example of a Performance
Monitor facility. It defines an architecture suitable for
performance monitoring facilities in the Embedded
environment. The architecture itself presents only programming
model visible features in conjunction with
architecturally defined behavioral features. Much of the
selection of events is by necessity implementationdependent
and is not described as part of the architecture;
however, this document provides guidelines for
some features of a performance monitor implementation
that should be followed by all implementations.
The example Performance Monitor facility provides the
ability to monitor and count predefined events such as
processor clocks, misses in the instruction cache or
data cache, types of instructions decoded, or mispredicted
branches. The count of such events can be used
to trigger the Performance Monitor exception. While
most of the specific events are not architected, the
mechanism of controlling data collection is.
The example Performance Monitor facility can be used
to do the following:
Improve system performance by monitoring software
execution and then recoding algorithms for
more efficiency. For example, memory hierarchy
behavior can be monitored and analyzed to optimize
task scheduling or data distribution algorithms.
Characterize processors in environments not easily
characterized by benchmarking.
Help system developers bring up and debug their
systems.
E.2 Programming Model
The example Performance Monitor facility defines a set
of Performance Monitor Registers (PMRs) that are
used to collect and control performance data collection
and an interrupt to allow intervention by software. The
PMRs provide various controls and access to collected
data. They are categorized as follows:
Counter registers. These registers are used for
data collection. The occurrence of selected events
are counted here. These registers are named
PMC0..15. User and supervisor level access to
these registers is through different PMR numbers
allowing different access rights.
Global controls. This register control global settings
of the Performance Monitor facility and affect
all counters. This register is named PMGC0. User
and supervisor level access to these registers is
through different PMR numbers allowing different
access rights. In addition, a bit in the MSR
(MSR PMM ) is defined to enable/disable counting.
Local controls. These registers control settings
that apply only to a particular counter. These registers
are named PMLCa0..15 and PMLCb0..15.
User and supervisor level access to these registers
is through different PMR numbers allowing different
access rights. Each set of local control
registers (PMLCan and PMLCbn) contains controls
that apply to the associated same numbered
counter register (e.g. PMLCa0 and PMLCb0 contain
controls for PMC0 while PMLCa1 and
PMLCb1 contain controls for PMC1).
Assembler Note
The counter registers, global controls, and local
controls have alias names which cause the assembler
to use different PMR numbers. The names
PMC0...15, PMGC0, PMLCa0...15, and
PMLCb0...15 cause the assembler to use the
supervisor level PMR number, and the names
UPMC0...15, UPMGC0, UPMLCa0...15, and
UPMLCb0...15 cause the assembler to use the
user-level PMR number.
A given implementation may implement fewer counter
registers (and their associated control registers) than
are architected. Architected counter and counter control
registers that are not implemented behave the
same as unarchitected Performance Monitor Registers.
PMRs are described in Section E.3.
Software uses the global and local controls to select
which events are counted in the counter registers,
when such events should be counted, and what action
Appendix E. Example Performance Monitor [Category: Embedded.Perfor-
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