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Version 2.03 Vector Shift Left Byte VX-form Vector Shift Left Halfword VX-form vslb VRT,VRA,VRB vslh VRT,VRA,VRB 4 VRT VRA VRB 260 0 6 11 16 21 31 do i=0 to 127 by 8 sh (VRB) i+5:i+7 VRT i:i+7 (VRA) i:i+7
Version 2.03 Vector Shift Right Algebraic Byte VX-form Vector Shift Right Algebraic Halfword VX-form vsrab VRT,VRA,VRB vsrah VRT,VRA,VRB 4 VRT VRA VRB 772 0 6 11 16 21 31 do i=0 to 127 by 8 sh (VRB) i+5:i+7 VRT i:i+7 (VRA) i:i+7 >> si sh For each vector element i from 0 to 15, do the following. Byte element i in VRA is shifted right by the number of bits specified in the low-order 3 bits of the corresponding byte element i in VRB. Bits shifted out of bit 7 of the byte element are lost. Bit 0 of the byte element is replicated to fill the vacated bits on the left. The result is placed into byte element i of VRT. Special Registers Altered: None 4 VRT VRA VRB 836 0 6 11 16 21 31 do i=0 to 127 by 16 sh (VRB) i+12:i+15 VRT i:i+15 (VRA) i:i+15 >> si sh For each vector element i from 0 to 7, do the following. Halfword element i in VRA is shifted right by the number of bits specified in the low-order 4 bits of the corresponding halfword element i in VRB. Bits shifted out of bit 15 of the halfword are lost. Bit 0 of the halfword is replicated to fill the vacated bits on the left. The result is placed into halfword element i of VRT. Special Registers Altered: None Vector Shift Right Algebraic Word VX-form vsraw VRT,VRA,VRB 4 VRT VRA VRB 900 0 6 11 16 21 31 do i=0 to 127 by 32 sh (VRB) i+27:i+31 VRT i:i+31 (VRA) i:i+31 >> si sh For each vector element i from 0 to 3, do the following. Word element i in VRA is shifted right by the number of bits specified in the low-order 5 bits of the corresponding word element i in VRB. Bits shifted out of bit 31 of the word are lost. Bit 0 of the word is replicated to fill the vacated bits on the left. The result is placed into word element i of VRT. Special Registers Altered: None Chapter 5. Vector Processor [Category: Vector] 181
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® Power ISA Version 2.03 September
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Version 2.03 Preface The roots of t
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Version 2.03 Table of Contents Pref
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Version 2.03 Chapter 5. Vector Proc
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Version 2.03 D.8 Move To/From Speci
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Version 2.03 5.7.1 32-Bit Mode . .
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Version 2.03 4.6 Invalid Real Addre
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Version 2.03 8.6 Debugger Notify Ha
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Version 2.03 5.8 Fixed-Point Select
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Version 2.03 Figures Preface ......
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Version 2.03 40. MMU Control and St
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Version 2.03 Book I: Power ISA User
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Version 2.03 Chapter 1. Introductio
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Version 2.03 GPR, FPR, or VR (e.g.
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Version 2.03 SPR(x) Special Purpose
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Version 2.03 An instruction in a ca
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Version 2.03 CR 32 63 “Condition
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Version 2.03 1.6.3 SC-FORM 0 6 11 1
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Version 2.03 1.6.19 EVX-FORM 0 6 11
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Version 2.03 SPR (11:20) Field used
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Version 2.03 for each virtual page,
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Version 2.03 beq done loop: cmplwi
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Version 2.03 Chapter 2. Branch Proc
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Version 2.03 or (RB) (unsigned comp
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Version 2.03 Programming Note Many
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Version 2.03 Branch I-form Branch C
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Version 2.03 2.5 Condition Register
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Version 2.03 2.6 System Call Instru
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Version 2.03 Chapter 3. Fixed-Point
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Version 2.03 3.2.3 Program Priority
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Version 2.03 Load Byte and Zero D-f
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Version 2.03 Load Halfword Algebrai
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Version 2.03 3.3.2.1 64-bit Fixed-P
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Version 2.03 3.3.3 Fixed-Point Stor
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Version 2.03 Store Word D-form Stor
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Version 2.03 3.3.4 Fixed-Point Load
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Version 2.03 3.3.6 Fixed-Point Move
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Version 2.03 Store String Word Imme
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Version 2.03 3.3.8 Fixed-Point Arit
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Version 2.03 Subtract From Immediat
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Version 2.03 Add to Zero Extended X
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Version 2.03 Divide Word XO-form di
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Version 2.03 Divide Doubleword XO-f
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Version 2.03 Compare Logical Immedi
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Version 2.03 3.3.10.1 64-bit Fixed-
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Version 2.03 OR Immediate Shifted D
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Version 2.03 NOR X-form Equivalent
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Version 2.03 3.3.12.1 64-bit Fixed-
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Version 2.03 Rotate Left Word Immed
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Version 2.03 3.3.13.1.1 64-bit Fixe
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Version 2.03 Rotate Left Doubleword
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Version 2.03 Shift Right Algebraic
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Version 2.03 3.3.14 Move To/From Sy
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Version 2.03 Move To Condition Regi
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Version 2.03 3.3.14.1 Move To/From
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Version 2.03 Chapter 4. Floating-Po
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Version 2.03 the FPRs with no conve
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Version 2.03 59 Floating-Point Zero
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Version 2.03 due to the invalid ope
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Version 2.03 Programming Note The F
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Version 2.03 When an exception occu
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Version 2.03 When Invalid Operation
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Version 2.03 4.4.5 Inexact Exceptio
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Version 2.03 4.5.2 Execution Model
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Version 2.03 Load Floating-Point Si
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Version 2.03 4.6.3 Floating-Point S
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Version 2.03 Store Floating-Point D
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Version 2.03 4.6.4 Floating-Point M
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Version 2.03 Floating Multiply [Sin
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Version 2.03 Floating Reciprocal Sq
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Version 2.03 Floating Negative Mult
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Version 2.03 Floating Convert To In
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Version 2.03 Floating Round to Inte
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Version 2.03 4.6.8 Floating-Point S
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Version 2.03 Move To FPSCR Bit 0 X-
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Page 161 and 162: Version 2.03 5.7.2 Vector Load Inst
Page 163 and 164: Version 2.03 5.7.3 Vector Store Ins
Page 165 and 166: Version 2.03 5.7.4 Vector Alignment
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Page 169 and 170: Version 2.03 Vector Unpack High Pix
Page 171 and 172: Version 2.03 5.8.2 Vector Merge Ins
Page 173 and 174: Version 2.03 5.8.3 Vector Splat Ins
Page 175 and 176: Version 2.03 5.8.6 Vector Shift Ins
Page 177 and 178: Version 2.03 5.9 Vector Integer Ins
Page 179 and 180: Version 2.03 Vector Add Unsigned By
Page 181 and 182: Version 2.03 Vector Subtract Unsign
Page 183 and 184: Version 2.03 5.9.1.3 Vector Integer
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Page 197 and 198: Version 2.03 5.9.2 Vector Integer C
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Page 217 and 218: Version 2.03 Chapter 6. Signal Proc
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Version 2.03 Initialize Accumulator
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Version 2.03 Vector Multiply Word L
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Version 2.03 Vector Multiply Word L
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Version 2.03 Vector Multiply Word S
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Version 2.03 Vector Multiply Word U
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Version 2.03 Vector Rotate Left Wor
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Version 2.03 Vector Shift Right Wor
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Version 2.03 Vector Store Word of T
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Version 2.03 Vector Subtract Unsign
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Version 2.03 Chapter 7. Embedded Fl
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Version 2.03 Denormalized numbers o
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Version 2.03 7.3 Embedded Floating-
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Version 2.03 Vector Floating-Point
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Version 2.03 Vector Floating-Point
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Version 2.03 Vector Convert Floatin
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Version 2.03 7.3.3 SPE.Embedded Flo
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Version 2.03 Floating-Point Single-
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Version 2.03 Floating-Point Single-
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Version 2.03 Convert Floating-Point
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Version 2.03 Floating-Point Double-
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Version 2.03 Floating-Point Double-
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Version 2.03 7.4 Embedded Floating-
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Version 2.03 Table 3: Embedded Floa
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Version 2.03 Table 7: Embedded Floa
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Version 2.03 Chapter 8. Legacy Move
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Version 2.03 Chapter 9. Legacy Inte
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Version 2.03 Multiply Accumulate Hi
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Version 2.03 Multiply Accumulate Lo
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Version 2.03 Multiply High Halfword
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Version 2.03 Negative Multiply Accu
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Version 2.03 Appendix A. Suggested
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Version 2.03 If FPSCR RN = 0b01 the
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Version 2.03 A.2 Floating-Point Con
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Version 2.03 Large Operand: FPSCR F
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Version 2.03 A.4 Floating-Point Rou
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Version 2.03 Appendix B. Vector RTL
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Version 2.03 Appendix C. Embedded F
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Version 2.03 C.3 Convert from Doubl
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Version 2.03 C.5 Convert to Single-
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Version 2.03 Appendix D. Assembler
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Version 2.03 D.2.3 Branch Mnemonics
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Version 2.03 D.4 Subtract Mnemonics
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Version 2.03 These codes are reflec
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Version 2.03 D.7.2 Operations on Wo
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Version 2.03 Load Address This mnem
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Version 2.03 Appendix E. Programmin
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Version 2.03 Multiple-precision shi
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Version 2.03 E.2.5 Conversion from
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Version 2.03 E.4 Vector Unaligned S
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Version 2.03 Book II: Power ISA Vir
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Version 2.03 Chapter 1. Storage Mod
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Version 2.03 Each program can acces
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Version 2.03 cause additional locat
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Version 2.03 1.7 Shared Storage Thi
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Version 2.03 Programming Note The f
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Version 2.03 Programming Note Becau
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Version 2.03 1.8.1 Concurrent Modif
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Version 2.03 Chapter 2. Effect of O
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Version 2.03 Chapter 3. Storage Con
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Version 2.03 3.2.2 Data Cache Instr
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Version 2.03 description assumes th
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Version 2.03 Programming Note This
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Version 2.03 Data Cache Block set t
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Version 2.03 3.2.2.1 Obsolete Data
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Version 2.03 Store Word Conditional
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Version 2.03 3.3.3 Memory Barrier I
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Version 2.03 Enforce In-order Execu
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Version 2.03 Chapter 4. Time Base 4
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Version 2.03 Programming Note Since
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Version 2.03 Chapter 5. External Co
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Version 2.03 Appendix A. Assembler
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Version 2.03 Appendix B. Programmin
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Version 2.03 B.2 Lock Acquisition a
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Version 2.03 B.3 List Insertion Thi
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Version 2.03 Book III-S: Power ISA
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Version 2.03 the execution of a Ve
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Version 2.03 Chapter 2. Logical Par
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Version 2.03 2.5 Logical Partition
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Version 2.03 3.3 Branch Processor I
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Version 2.03 4.3.5 Software-use SPR
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Version 2.03 4.4.2 OR Instruction o
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Version 2.03 Move To Special Purpos
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Version 2.03 Move To Machine State
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Version 2.03 stream being executed)
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Version 2.03 5.7.2.3 Storage Contro
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Version 2.03 5.7.5 Virtual Address
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Version 2.03 5.7.6 Virtual to Real
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Version 2.03 A virtual page is mapp
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Version 2.03 The 62-bit real addres
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Version 2.03 not necessarily perfor
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Version 2.03 5.8 Storage Control At
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Version 2.03 5.9 Storage Control In
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Version 2.03 information used in ad
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Version 2.03 SLB Move From Entry VS
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Version 2.03 Move To Segment Regist
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Version 2.03 5.9.3.3 TLB Management
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Version 2.03 TLB Invalidate All tlb
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Version 2.03 Programming Note The e
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Version 2.03 Chapter 6. Interrupts
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Version 2.03 6.3 Interrupt Synchron
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Version 2.03 Programming Note For i
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Version 2.03 6.5 Interrupt Definiti
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Version 2.03 If the contents of the
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Version 2.03 to fetch a branch targ
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Version 2.03 Programming Note These
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Version 2.03 Execution resumes at e
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Version 2.03 6.8 Interrupt Prioriti
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Version 2.03 Chapter 7. Timer Facil
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Version 2.03 “Assembler Extended
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Version 2.03 Chapter 8. Debug Facil
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Version 2.03 Programming Note Proce
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Version 2.03 Chapter 9. External Co
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Version 2.03 Chapter 10. Synchroniz
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Version 2.03 Notes: 1. The effect o
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Version 2.03 Appendix A. Assembler
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Version 2.03 Appendix B. Example Pe
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Version 2.03 reflected in Performan
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Version 2.03 Programming Note Time
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Version 2.03 32 Contents of SIAR an
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Version 2.03 Appendix C. Example Tr
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Version 2.03 Appendix D. Interpreta
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Version 2.03 Book III-E: Power ISA
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Version 2.03 1.6 Synchronization Th
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Version 2.03 2.3 Branch Processor I
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Version 2.03 Return From Machine-Ch
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Version 2.03 3.3.4 External Process
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Version 2.03 3.4 Fixed-Point Proces
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Version 2.03 Move To Special Purpos
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Version 2.03 Move From Device Contr
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Version 2.03 3.4.2 External Process
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Version 2.03 Store Byte by External
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Version 2.03 Data Cache Block Store
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Version 2.03 Data Cache Block Touch
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Version 2.03 Load Floating-Point Do
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Version 2.03 Load Vector by Externa
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Version 2.03 4.6 Invalid Real Addre
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Version 2.03 SX Supervisor State Ex
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Version 2.03 MSR DS for data storag
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Version 2.03 4.7.4 Storage Access C
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Version 2.03 Programming Note This
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Version 2.03 Accesses to the same s
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Version 2.03 4.9.2 Cache Locking [C
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Version 2.03 4.9.2.3 Cache Locking
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Version 2.03 4.9.3 Synchronize Inst
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Version 2.03 TLB Search Indexed X-f
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Version 2.03 Chapter 5. Interrupts
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Version 2.03 5.2.3 Critical Save/Re
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Version 2.03 5.2.9 Exception Syndro
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Version 2.03 5.2.11.1 Machine Check
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Version 2.03 exception that generat
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Version 2.03 Programming Note For i
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Version 2.03 IVOR Interrupt Excepti
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Version 2.03 5.6.3 Data Storage Int
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Version 2.03 cessing system. Also,
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Version 2.03 MSR CM MSR CM is set t
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Version 2.03 CSRR0, CSRR1, MSR, and
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Version 2.03 5.6.17 SPE/Embedded Fl
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Version 2.03 5.6.21 Processor Doorb
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Version 2.03 5.8 Interrupt Ordering
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Version 2.03 5.8.2 Interrupt Order
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Version 2.03 5.9.1.5 Exception Prio
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Version 2.03 Chapter 6. Reset and I
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Version 2.03 Chapter 7. Timer Facil
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Version 2.03 7.3 Decrementer The De
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Version 2.03 Bit(s) Description 32:
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Version 2.03 Time-out. No exception
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Version 2.03 Chapter 8. Debug Facil
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Version 2.03 Programming Note There
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Version 2.03 Later, if the debug ex
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Version 2.03 whose direction will b
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Version 2.03 8.4.10 Critical Interr
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Version 2.03 34:35 Instruction Addr
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Version 2.03 40:41 Data Address Com
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Version 2.03 8.5.3 Instruction Addr
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Version 2.03 Chapter 9. Processor C
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Version 2.03 9.3 Processor Control
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Version 2.03 Chapter 10. Synchroniz
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Version 2.03 If an mtmsr, wrtee, or
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Version 2.03 Appendix A. Implementa
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Version 2.03 A.2.1.3 Instruction Ca
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Version 2.03 Instruction Cache Read
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Version 2.03 Appendix B. Assembler
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Version 2.03 Appendix C. Guidelines
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Version 2.03 Appendix D. Type FSL S
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Version 2.03 52:63 Next Victim (NV)
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Version 2.03 58 Default VLE Value (
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Version 2.03 D.2.5 MMU Configuratio
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Version 2.03 D.4.3 Invalidating TLB
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Version 2.03 D.6 Type FSL MMU Instr
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Version 2.03 TLB Synchronize XL-for
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Version 2.03 Appendix E. Example Pe
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Version 2.03 counter with an event
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Version 2.03 111 Threshold field is
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Version 2.03 E.5 Performance Monito
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Version 2.03 Book VLE: Power ISA Op
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Version 2.03 Chapter 1. Variable Le
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Version 2.03 1.4.6 R-form (16-bit M
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Version 2.03 UI (6:10 || 21:31, 11:
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Version 2.03 Chapter 2. VLE Storage
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Version 2.03 ESR MIF is set when an
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Version 2.03 Chapter 3. VLE Compati
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Version 2.03 Chapter 4. Branch Oper
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Version 2.03 4.2 Branch Instruction
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Version 2.03 Branch to Count Regist
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Version 2.03 Return From Machine Ch
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Version 2.03 4.4 Condition Register
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Version 2.03 Load Halfword Algebrai
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Version 2.03 5.2 Fixed-Point Store
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Version 2.03 Store Word D-form Stor
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Version 2.03 5.5 Fixed-Point Arithm
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Version 2.03 Add Scaled Immediate C
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Version 2.03 5.6 Fixed-Point Compar
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Version 2.03 Compare Logical Scaled
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Version 2.03 Compare Halfword Logic
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Version 2.03 OR (two operand) Immed
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Version 2.03 Extend Sign Byte Short
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Version 2.03 5.10 Fixed-Point Rotat
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Version 2.03 Shift Right Algebraic
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Version 2.03 Chapter 7. Additional
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Version 2.03 Appendix A. VLE Instru
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Version 2.03 Form Mode Dep. 1 Priv
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Version 2.03 Appendix B. VLE Instru
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Version 2.03 Appendices: Power ISA
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Version 2.03 Appendix A. Incompatib
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Version 2.03 In POWER bits 20:26
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Version 2.03 privilege: mfsr and mf
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Version 2.03 A.32 POWER2 Compatibil
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Version 2.03 Appendix B. Platform S
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Version 2.03 Appendix C. Complete S
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Version 2.03 decimal SPR 1 Register
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Version 2.03 Appendix D. Illegal In
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Version 2.03 Appendix E. Reserved I
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Version 2.03 Appendix F. Opcode Map
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Version 2.03 Table 2: Extended opco
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Version 2.03 Table 5 (Left-Center)
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Version 2.03 Table 5 (Right) Extend
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Version 2.03 Table 6 (Left-Center)
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Version 2.03 Table 6 (Right) Extend
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Version 2.03 Table 7. (Right) Exten
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Version 2.03 Table 8. (Right) Exten
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Version 2.03 761
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Version 2.03 763 Table 13. (Right)
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Version 2.03 765 Table 14. (Right)
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Version 2.03 Appendix G. Power ISA
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Version 2.03 Form Opcode Pri Ext Mo
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Version 2.03 Appendix H. Power ISA
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Version 2.03 Appendix I. Power ISA
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Version 2.03 Mode Dependency and Pr
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Version 2.03 Index A a bit 26 A-for
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Version 2.03 F FE 25, 92 FEX 91 FE0
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Version 2.03 instructions classes 1
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Version 2.03 Machine Status Save Re
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