Power ISA™ Version 2.03 - Power.org

Version 2.03
mented by one. For the leading-zero case, the significand
is shifted left while decrementing its exponent by
one for each bit shifted, until the leading significand bit
becomes one. The Guard bit and the Round bit (see
Section 4.5.1, “Execution Model for IEEE Operations”
on page 103) participate in the shift with zeros shifted
into the Round bit. The exponent is regarded as if its
range were unlimited.
After normalization, or if normalization was not
required, the intermediate result may have a nonzero
significand and an exponent value that is less than the
minimum value that can be represented in the format
specified for the result. In this case, the intermediate
result is said to be “Tiny” and the stored result is determined
by the rules described in Section 4.4.4, “Underflow
Exception”. These rules may require
denormalization.
A number is denormalized by shifting its significand
right while incrementing its exponent by 1 for each bit
shifted, until the exponent is equal to the format’s minimum
value. If any significant bits are lost in this shifting
process then “Loss of Accuracy” has occurred (See
Section 4.4.4, “Underflow Exception” on page 102) and
Underflow Exception is signaled.
4.3.5 Data Handling and Precision
Most of the Floating-Point Processor Architecture,
including all computational, Move, and Select instructions,
use the floating-point double format to represent
data in the FPRs. Single-precision and integer-valued
operands may be manipulated using double-precision
operations. Instructions are provided to coerce these
values from a double format operand. Instructions are
also provided for manipulations which do not require
double-precision. In addition, instructions are provided
to access a true single-precision representation in storage,
and a fixed-point integer representation in GPRs.
4.3.5.1 Single-Precision Operands
For single format data, a format conversion from single
to double is performed when loading from storage into
an FPR and a format conversion from double to single
is performed when storing from an FPR to storage. No
floating-point exceptions are caused by these instructions.
An instruction is provided to explicitly convert a
double format operand in an FPR to single-precision.
Floating-point single-precision is enabled with four
types of instruction.
2. Round to Floating-Point Single-Precision
The Floating Round to Single-Precision instruction
rounds a double-precision operand to single-precision,
checking the exponent for single-precision
range and handling any exceptions according to
respective enable bits, and places that operand
into an FPR in double format. For results produced
by single-precision arithmetic instructions, single-precision
loads, and other instances of the
Floating Round to Single-Precision instruction, this
operation does not alter the value.
3. Single-Precision Arithmetic Instructions
This form of instruction takes operands from the
FPRs in double format, performs the operation as
if it produced an intermediate result having infinite
precision and unbounded exponent range, and
then coerces this intermediate result to fit in single
format. Status bits, in the FPSCR and optionally in
the Condition Register, are set to reflect the single-precision
result. The result is then converted to
double format and placed into an FPR. The result
lies in the range supported by the single format.
All input values must be representable in single
format; if they are not, the result placed into the target
FPR, and the setting of status bits in the
FPSCR and in the Condition Register (if Rc=1),
are undefined.
4. Store Floating-Point Single
This form of instruction converts a double-precision
operand to single format and stores that operand
into storage. No floating-point exceptions are
caused by these instructions. (The value being
stored is effectively assumed to be the result of an
instruction of one of the preceding three types.)
When the result of a Load Floating-Point Single, Floating
Round to Single-Precision, or single-precision arithmetic
instruction is stored in an FPR, the low-order 29
FRACTION bits are zero.
1. Load Floating-Point Single
This form of instruction accesses a single-precision
operand in single format in storage, converts it
to double format, and loads it into an FPR. No
floating-point exceptions are caused by these
instructions.
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Power ISA -- Book I