Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Load Double into Two Words
EVX-form
Vector Load Double into Two Words
Indexed
EVX-form
evldw
RT,D(RA)
evldwx
RT,RA,RB
4 RT RA UI 771
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + EXTZ(UI×8)
RT 0:31 MEM(EA, 4)
RT 32:63 MEM(EA+4, 4)
D in the instruction mnemonic is UI × 8. The doubleword
addressed by EA is loaded from memory and
placed in RT.
Special Registers Altered:
None
4 RT RA RB 770
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + (RB)
RT 0:31 MEM(EA, 4)
RT 32:63 MEM(EA+4, 4)
The doubleword addressed by EA is loaded from memory
and placed in RT.
Special Registers Altered:
None
Vector Load Halfword into Halfwords
Even and Splat
EVX-form
evlhhesplat RT,D(RA)
4 RT RA UI 777
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + EXTZ(UI×2)
RT 0:15 MEM(EA,2)
RT 16:31 0x0000
RT 32:47 MEM(EA,2)
RT 48:63 0x0000
D in the instruction mnemonic is UI × 2. The halfword
addressed by EA is loaded from memory and placed in
the even halfwords of each element of RT. The odd
halfwords of each element of RT are set to 0.
Special Registers Altered:
None
Vector Load Halfword into Halfwords
Even and Splat Indexed EVX-form
evlhhesplatx RT,RA,RB
4 RT RA RB 776
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + (RB)
RT 0:15 MEM(EA,2)
RT 16:31 0x0000
RT 32:47 MEM(EA,2)
RT 48:63 0x0000
The halfword addressed by EA is loaded from memory
and placed in the even halfwords of each element of
RT. The odd halfwords of each element of RT are set to
0.
Special Registers Altered:
None
Chapter 6. Signal Processing Engine (SPE)
209