Power ISA™ Version 2.03 - Power.org

Version 2.03
4.6.5.2 Floating-Point Multiply-Add Instructions
These instructions combine a multiply and an add operation
without an intermediate rounding operation. The
fraction part of the intermediate product is 106 bits wide
(L bit, FRACTION), and all 106 bits take part in the add/
subtract portion of the instruction.
Status bits are set as follows.
Overflow, Underflow, and Inexact Exception bits,
the FR and FI bits, and the FPRF field are set
based on the final result of the operation, and not
on the result of the multiplication.
Invalid Operation Exception bits are set as if the
multiplication and the addition were performed
using two separate instructions (fmul[s], followed
by fadd[s] or fsub[s]). That is, multiplication of
infinity by 0 or of anything by an SNaN, and/or
addition of an SNaN, cause the corresponding
exception bits to be set.
Floating Multiply-Add [Single]
A-form
Floating Multiply-Subtract [Single] A-form
fmadd FRT,FRA,FRC,FRB (Rc=0)
fmadd. FRT,FRA,FRC,FRB (Rc=1)
63 FRT FRA FRB FRC 29 Rc
0 6 11 16 21 26 31
fmsub FRT,FRA,FRC,FRB (Rc=0)
fmsub. FRT,FRA,FRC,FRB (Rc=1)
63 FRT FRA FRB FRC 28 Rc
0 6 11 16 21 26 31
fmadds FRT,FRA,FRC,FRB (Rc=0)
fmadds. FRT,FRA,FRC,FRB (Rc=1)
59 FRT FRA FRB FRC 29 Rc
0 6 11 16 21 26 31
fmsubs FRT,FRA,FRC,FRB (Rc=0)
fmsubs. FRT,FRA,FRC,FRB (Rc=1)
59 FRT FRA FRB FRC 28 Rc
0 6 11 16 21 26 31
The operation
FRT [(FRA)×(FRC)] + (FRB)
is performed.
The floating-point operand in register FRA is multiplied
by the floating-point operand in register FRC. The
floating-point operand in register FRB is added to this
intermediate result.
If the most significant bit of the resultant significand is
not 1, the result is normalized. The result is rounded to
the target precision under control of the Floating-Point
Rounding Control field RN of the FPSCR and placed
into register FRT.
FPSCR FPRF is set to the class and sign of the result,
except for Invalid Operation Exceptions when
FPSCR VE =1.
The operation
FRT [(FRA)×(FRC)] - (FRB)
is performed.
The floating-point operand in register FRA is multiplied
by the floating-point operand in register FRC. The
floating-point operand in register FRB is subtracted
from this intermediate result.
If the most significant bit of the resultant significand is
not 1, the result is normalized. The result is rounded to
the target precision under control of the Floating-Point
Rounding Control field RN of the FPSCR and placed
into register FRT.
FPSCR FPRF is set to the class and sign of the result,
except for Invalid Operation Exceptions when
FPSCR VE =1.
Special Registers Altered:
FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1
(if Rc=1)
Special Registers Altered:
FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1
(if Rc=1)
118
Power ISA -- Book I