Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Multiply Halfwords, Even, Signed,
Saturate, Fractional and Accumulate into
Words
EVX-form
evmhessfaaw RT,RA,RB
4 RT RA RB 1283
0 6 11 16 21 31
Vector Multiply Halfwords, Even, Signed,
Saturate, Fractional and Accumulate
Negative into Words
EVX-form
evmhessfanw RT,RA,RB
4 RT RA RB 1411
0 6 11 16 21 31
temp 0:31 (RA) 0:15 × sf (RB) 0:15
if ((RA) 0:15 = 0x8000) & ((RB) 0:15 = 0x8000) then
temp 0:31 0x7FFF_FFFF
movh 1
else
movh 0
temp 0:63 EXTS((ACC) 0:31 ) + EXTS(temp 0:31 )
ovh (temp 31 ⊕ temp 32 )
RT 0:31 SATURATE(ovh, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
temp 0:31 (RA) 32:47 × sf (RB) 32:47
if ((RA) 32:47 = 0x8000) & ((RB) 32:47 = 0x8000) then
temp 0:31 0x7FFF_FFFF
movl 1
else
movl 0
temp 0:63 EXTS((ACC) 32:63 ) + EXTS(temp 0:31 )
ovl (temp 31 ⊕ temp 32 )
RT 32:63 SATURATE(ovl, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh | movh
SPEFSCR OV ovl| movl
SPEFSCR SOVH SPEFSCR SOVH | ovh | movh
SPEFSCR SOV SPEFSCR SOV | ovl| movl
The corresponding even-numbered halfword signed
fractional elements in RA and RB are multiplied producing
a 32-bit product. If both inputs are -1.0, the result
saturates to 0x7FFF_FFFF. Each 32-bit product is then
added to the corresponding word in the accumulator
saturating if overflow occurs, and the result is placed in
RT and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
temp 0:31 (RA) 0:15 × sf (RB) 0:15
if ((RA) 0:15 = 0x8000) & ((RB) 0:15 = 0x8000) then
temp 0:31 0x7FFF_FFFF
movh 1
else
movh 0
temp 0:63 EXTS((ACC) 0:31 ) - EXTS(temp 0:31 )
ovh (temp 31 ⊕ temp 32 )
RT 0:31 SATURATE(ovh, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
temp 0:31 (RA) 32:47 × sf (RB) 32:47
if ((RA) 32:47 = 0x8000) & ((RB) 32:47 = 0x8000) then
temp 0:31 0x7FFF_FFFF
movl 1
else
movl 0
temp 0:63 EXTS((ACC) 32:63 ) - EXTS(temp 0:31 )
ovl (temp 31 ⊕ temp 32 )
RT 32:63 SATURATE(ovl, temp 31 , 0x8000_0000,
0x7FFF_FFFF, temp 32:63 )
ACC 0:63 (RT) 0:63
SPEFSCR OVH ovh | movh
SPEFSCR OV ovl| movl
SPEFSCR SOVH SPEFSCR SOVH | ovh | movh
SPEFSCR SOV SPEFSCR SOV | ovl| movl
The corresponding even-numbered halfword signed
fractional elements in RA and RB are multiplied producing
a 32-bit product. If both inputs are -1.0, the result
saturates to 0x7FFF_FFFF. Each 32-bit product is then
subtracted from the corresponding word in the accumulator
saturating if overflow occurs, and the result is
placed in RT and the accumulator.
Special Registers Altered:
ACC, OV, OVH, SOV, SOVH
Chapter 6. Signal Processing Engine (SPE)
219