Power ISA™ Version 2.03 - Power.org

Version 2.03
interrupt is then taken and the destination register is not
updated.
7.2.3.6 Default Results
Default results are generated when an Embedded
Floating-Point Invalid Operation/Input Error, Embedded
Floating-Point Overflow, Embedded Floating-Point
Underflow, or Embedded Floating-Point Divide by Zero
occurs on an Embedded Floating-Point operation.
Default results provide a normalized value as a result of
the operation. In general, Denorm results and underflows
are set to 0 and overflows are saturated to the
maximum representable number.
Default results produced for each operation are
described in Section 7.4, “Embedded Floating-Point
Results Summary”.
7.2.4 IEEE 754 Compliance
The Embedded Floating-Point categories require a
floating-point system as defined in the ANSI/IEEE Standard
754-1985 but may rely on software support in
order to conform fully with the standard. Thus, whenever
an input operand of the Embedded Floating-Point
instruction has data values that are +Infinity, -Infinity,
Denormalized, NaN, or when the result of an operation
produces an overflow or an underflow, an Embedded
Floating-Point Data interrupt may be taken and the
interrupt handler is responsible for delivering IEEE 754
compliant behavior if desired.
When Embedded Floating-Point Invalid Operation/
Input Error exceptions are disabled (SPEFSCR FINVE =
0), default results are provided by the hardware when
an Infinity, Denormalized, or NaN input is received, or
for the operation 0/0. When Embedded Floating-Point
Underflow exceptions are disabled (SPEFSCR FUNFE =
0) and the result of a floating-point operation underflows,
a signed zero result is produced. The Embedded
Floating-Point Round (Inexact) exception is also signaled
for this condition. When Embedded Floating-Point
Overflow exceptions are disabled
(SPEFSCR FOVFE = 0) and the result of a floating-point
operation overflows, a pmax or nmax result is produced.
The Embedded Floating-Point Round (Inexact)
exception is also signaled for this condition. An exception
enable flag (SPEFSCR FINXE ) is also provided for
generating an Embedded Floating-Point Round interrupt
when an inexact result is produced, to allow a software
handler to conform to the IEEE 754 standard. An
Embedded Floating-Point Divide By Zero exception
enable flag (SPEFSCR FDBZE ) is provided for generating
an Embedded Floating-Point Data interrupt when a
divide by zero operation is attempted to allow a software
handler to conform to the IEEE 754 standard. All
of these exceptions may be disabled, and the hardware
will then deliver an appropriate default result.
The sign of the result of an addition operation is the
sign of the source operand having the larger absolute
value. If both operands have the same sign, the sign of
the result is the same as the sign of the operands. This
includes subtraction which is addition with the negation
of the sign of the second operand. The sign of the
result of an addition operation with operands of differing
signs for which the result is zero is positive except
when rounding to negative infinity. Thus -0 + -0 = -0,
and all other cases which result in a zero value give +0
unless the rounding mode is round to negative infinity.
Programming Note
Note that when exceptions are disabled and default
results computed, operations having input values
that are denormalized may provide different results
on different implementations. An implementation
may choose to use the denormalized value or a
zero value for any computation. Thus a computational
operation involving a denormalized value and
a normal value may return different results depending
on the implementation.
7.2.4.1 Sticky Bit Handling For Exception
Conditions
The SPEFSCR register defines sticky bits for retaining
information about exception conditions that are
detected. There are 5 sticky bits (FINXS, FINVS,
FDBZS, FUNFS and FOVFS) that can be used to help
provide IEEE 754 compliance. The sticky bits represent
the combined ‘or’ of all the previous status bits produced
from any Embedded Floating-Point operation
since the last time software zeroed the sticky bit. The
hardware will never set a sticky bit to 0.
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Power ISA -- Book I