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Power ISA™ Version 2.03 - Power.org

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<strong>Version</strong> <strong>2.03</strong><br />

6.2 Cache Management Instructions<br />

Cache management instructions implemented by category<br />

VLE are identical to those defined in Books II and<br />

III.<br />

The Cache Management instructions from Book II,<br />

dcba, dcbf, dcbst, dcbt, dcbtst, dcbz, icbi, and icbt<br />

are available while executing in VLE mode. The mnemonics,<br />

decoding, and semantics for these instructions<br />

are identical to those in Book II; see Section 3.2 of<br />

Book II for the instruction definitions.<br />

The Cache Management instruction from Book III, dcbi<br />

is available while executing in VLE mode. The mnemonics,<br />

decoding, and semantics for this instruction<br />

are identical to those in Book III; see Section 4.9.1 of<br />

Book III-E for the instruction definition.<br />

6.5 Instruction Alignment and<br />

Byte Ordering<br />

Only Big-Endian instruction memory is supported when<br />

executing from a page of VLE instructions. Attempting<br />

to fetch VLE instructions from a page marked as Little-<br />

Endian generates an instruction storage interrupt byteordering<br />

exception.<br />

6.3 Cache Locking Instructions<br />

Cache locking instructions implemented by category<br />

VLE are identical to those defined in Book III. If the<br />

Cache Locking instructions are implemented in category<br />

VLE, the category Embedded.Cache Locking<br />

must also be implemented.<br />

The Cache Locking instructions from Book III, dcbtls,<br />

dcbtstls, dcblc, icbtls, and icblc are available while<br />

executing in VLE mode. The mnemonics, decoding,<br />

and semantics for these instructions are identical to<br />

those in Book III; Section 4.9.2 of Book III-E for the<br />

instruction definitions.<br />

6.4 TLB Management Instructions<br />

The TLB management instructions implemented by<br />

category VLE are identical to those defined in Book III.<br />

The TLB Management instructions from Book III, tlbre,<br />

tlbwe, tlbivax, tlbsync, and tlbsx are available while<br />

executing in VLE mode. The mnemonics, decoding,<br />

and semantics for these instructions are identical to<br />

those in Book III. See Section 4.9.4.1 of Book III-E for<br />

the instruction definitions.<br />

Instructions and resources from category Embedded.MMU<br />

Type FSL are available if the appropriate category<br />

is implemented.<br />

690<br />

<strong>Power</strong> ISA -- Book VLE

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