Power ISA™ Version 2.03 - Power.org

Version 2.03
A.2 Embedded Cache Debug Facility
[Category: Embedded.Cache Debug]
A.2.1 Embedded Cache Debug Registers
A.2.1.1
High
Data Cache Debug Tag Register
The Data Cache Debug Tag Register High (DCDBTRH)
is a 32-bit Special Purpose Register (SPRN=0x39D).
Data Cache Debug Tag Register High is read using
mfspr and is set by dcread.
DCDBTRH
32 63
Figure 25. Data Cache Debug Tag Register High
Programming Note
An example implementation of DCDBTRH could
have the following content and format.
Bit(s) Description
32:55 Tag Real Address (TRA)
Bits 0:23 of the lower 32 bits of the 36-bit
real address associated with this cache
block
56 Valid (V)
The valid indicator for the cache block (1
indicates valid)
57:59 Reserved
60:63 Tag Extended Real Address (TERA)
Upper 4 bits of the 36-bit real address
associated with this cache block
Implementations may support different content and
format based on their cache implementation.
A.2.1.2
Low
Data Cache Debug Tag Register
The Data Cache Debug Tag Register Low (DCDBTRL)
is a 32-bit Special Purpose Register (SPRN=0x39C).
Data Cache Debug Tag Register Low is read using
mfspr and is set by dcread.
DCDBTRL
32 63
Figure 26. Data Cache Debug Tag Register Low
Programming Note
An example implementation of DCDBTRL could
have the following content and format.
Bit(s) Description
32:44 Reserved (TRA)
45 U bit parity (UPAR)
46:47 Tag parity (TPAR)
48:51 Data parity (DPAR)
52:55 Modified (dirty) parity (MPAR)
56:59 Dirty Indicators (D)
The “dirty” (modified) indicators for each
of the four doublewords in the cache block
60 U0 Storage Attribute (U0)
The U0 storage attribute for the page
associated with this cache block
61 U1 Storage Attribute (U1)
The U1 storage attribute for the page
associated with this cache block
62 U2 Storage Attribute (U2)
The U2 storage attribute for the page
associated with this cache block
63 U3 Storage Attribute (U3)
The U3 storage attribute for the page
associated with this cache block
Implementations may support different content and
format based on their cache implementation.
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Power ISA -- Book III-E