Power ISA™ Version 2.03 - Power.org

Version 2.03
[Category: Embedded.Enhanced Debug] will contain
the address of the instruction after the one which
enabled the Debug interrupt by setting MSR DE to 1.
Software in the Debug interrupt handler can observe
the DBSR IDE bit to determine how to interpret the value
in CSRR0/DSRR0 [Category: Embedded.Enhanced
Debug.
8.4.7 Return Debug Event
A Return debug event (RET) occurs if DBCR0 RET =1
and an attempt is made to execute an rfi. Return debug
events can occur regardless of the setting of MSR DE .
When a Return debug event occurs, DBSR RET is set to
1 to record the debug exception. If MSR DE =0, DBSR IDE
is also set to 1 to record the imprecise debug event.
If MSR DE =1 at the time of the Return Debug event, a
Debug interrupt will occur immediately, and CSRR0/
DSRR0 [Category: Embedded.Enhanced Debug will be
set to the address of the rfi.
If MSR DE =0 at the time of the Return Debug event, a
Debug interrupt will not occur.
Later, if the Debug exception has not been reset by
clearing DBSR RET , and MSR DE is set to 1, a delayed
imprecise Debug interrupt will occur. In this case,
CSRR0/DSRR0 [Category: Embedded.Enhanced
Debug will contain the address of the instruction after
the one which enabled the Debug interrupt by setting
MSR DE to 1. An imprecise Debug interrupt can be
caused by executing an rfi when DBCR0 RET =1 and
MSR DE =0, and the execution of that rfi happens to
cause MSR DE to be set to 1. Software in the Debug
interrupt handler can observe the DBSR IDE bit to determine
how to interpret the value in CSRR0/DSRR0 [Category:
Embedded.Enhanced Debug].
8.4.8 Unconditional Debug Event
An Unconditional debug event (UDE) occurs when the
Unconditional Debug Event (UDE) signal is activated
by the debug mechanism. The exact definition of the
UDE signal and how it is activated is implementationdependent.
The Unconditional debug event is the only
debug event which does not have a corresponding
enable bit for the event in DBCR0 (hence the name of
the event). The Unconditional debug event can occur
regardless of the setting of MSR DE .
When an Unconditional debug event occurs, the
DBSR UDE bit is set to 1 to record the Debug exception.
If MSR DE =0, DBSR IDE is also set to 1 to record the
imprecise debug event.
If MSR DE =1 (i.e. Debug interrupts are enabled) at the
time of the Unconditional Debug exception, a Debug
interrupt will occur immediately (provided there exists
no higher priority exception which is enabled to cause
an interrupt), and CSRR0/DSRR0 [Category: Embedded.Enhanced
Debug] will be set to the address of the
instruction which would have executed next had the
interrupt not occurred.
If MSR DE =0 (i.e. Debug interrupts are disabled) at the
time of the Unconditional Debug exception, a Debug
interrupt will not occur.
Later, if the Unconditional Debug exception has not
been reset by clearing DBSR UDE , and MSR DE is set to
1, a delayed Debug interrupt will occur. In this case,
CSRR0/DSRR0 [Category: Embedded.Enhanced
Debug] will contain the address of the instruction after
the one which enabled the Debug interrupt by setting
MSR DE to 1. Software in the Debug interrupt handler
can observe DBSR IDE to determine how to interpret the
value in CSRR0/DSRR0 [Category: Embedded.Enhanced
Debug].
8.4.9 Critical Interrupt Taken
Debug Event [Category: Embedded.Enhanced
Debug]
A Critical Interrupt Taken debug event (CIRPT) occurs
if DBCR0 CIRPT = 1 (i.e. Critical Interrupt Taken debug
events are enabled) and a critical interrupt occurs. A
critical interrupt is any interrupt that saves state in
CSRR0 and CSRR1 when the interrupt is taken. Critical
Interrupt Taken debug events can occur regardless of
the setting of MSR DE .
When a Critical Interrupt Taken debug event occurs,
DBSR CIRPT is set to 1 to record the debug event. If
MSR DE =0, DBSR IDE is also set to 1 to record the
imprecise debug event.
If MSR DE = 1 (i.e. Debug Interrupts are enabled) at the
time of the Critical Interrupt Taken debug event, a
Debug Interrupt will occur immediately (provided there
is no higher priority exception which is enabled to
cause an interrupt), and DSRR0 will be set to the
address of the first instruction of the critical interrupt
handler. No instructions at the critical interrupt handler
will have been executed.
If MSR DE = 0 (i.e. Debug Interrupts are disabled) at the
time of the Critical Interrupt Taken debug event, a
Debug Interrupt will not occur, and the handler for the
critical interrupt which caused the debug event will be
allowed to execute normally. Later, if the debug exception
has not been reset by clearing DBSR CIRPT and
MSR DE is set to 1, a delayed Debug Interrupt will occur.
In this case DSRR0 will contain the address of the
instruction after the one that set MSR DE = 1. Software
in the Debug Interrupt handler can observe DBSR IDE to
determine how to interpret the value in DSRR0.
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Power ISA -- Book III-E