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Power ISA™ Version 2.03 - Power.org

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<strong>Version</strong> <strong>2.03</strong><br />

Vector Multiply Halfwords, Odd, Signed,<br />

Modulo, Fractional and Accumulate into<br />

Words<br />

EVX-form<br />

evmhosmfaaw RT,RA,RB<br />

4 RT RA RB 1295<br />

0 6 11 16 21 31<br />

Vector Multiply Halfwords, Odd, Signed,<br />

Modulo, Fractional and Accumulate<br />

Negative into Words<br />

EVX-form<br />

evmhosmfanw RT,RA,RB<br />

4 RT RA RB 1423<br />

0 6 11 16 21 31<br />

temp 0:31 (RA) 16:31 × sf (RB) 16:31<br />

RT 0:31 (ACC) 0:31 + temp 0:31<br />

temp 0:31 (RA) 48:63 × sf (RB) 48:63<br />

RT 32:63 (ACC) 32:63 + temp 0:31<br />

ACC 0:63 (RT) 0:63<br />

For each word element in the accumulator, the corresponding<br />

odd-numbered halfword signed fractional elements<br />

in RA and RB are multiplied. The 32 bits of each<br />

intermediate product are added to the contents of the<br />

corresponding accumulator word and the results are<br />

placed into the corresponding RT words and into the<br />

accumulator.<br />

Special Registers Altered:<br />

ACC<br />

temp 0:31 (RA) 16:31 × sf (RB) 16:31<br />

RT 0:31 (ACC) 0:31 - temp 0:31<br />

temp 0:31 (RA) 48:63 × sf (RB) 48:63<br />

RT 32:63 (ACC) 32:63 - temp 0:31<br />

ACC 0:63 (RT) 0:63<br />

For each word element in the accumulator, the corresponding<br />

odd-numbered halfword signed fractional elements<br />

in RA and RB are multiplied. The 32 bits of each<br />

intermediate product are subtracted from the contents<br />

of the corresponding accumulator word and the results<br />

are placed into the corresponding RT words and into<br />

the accumulator.<br />

Special Registers Altered:<br />

ACC<br />

Vector Multiply Halfwords, Odd, Signed,<br />

Modulo, Integer<br />

EVX-form<br />

Vector Multiply Halfwords, Odd, Signed,<br />

Modulo, Integer to AccumulatorEVX-form<br />

evmhosmi<br />

RT,RA,RB<br />

evmhosmia RT,RA,RB<br />

4 RT RA RB 1037<br />

0 6 11 16 21 31<br />

4 RT RA RB 1069<br />

0 6 11 16 21 31<br />

RT 0:31 (RA) 16:31 × si (RB) 16:31<br />

RT 32:63 (RA) 48:63 × si (RB) 48:63<br />

The corresponding odd-numbered halfword<br />

signed-integer elements in RA and RB are multiplied.<br />

The two 32-bit products are placed into the corresponding<br />

words of RT.<br />

Special Registers Altered:<br />

None<br />

RT 0:31 (RA) 16:31 × si (RB) 16:31<br />

RT 32:63 (RA) 48:63 × si (RB) 48:63<br />

ACC 0:63 (RT) 0:63<br />

The corresponding odd-numbered halfword<br />

signed-integer elements in RA and RB are multiplied.<br />

The two 32-bit products are placed into the corresponding<br />

words of RT and into the accumulator.<br />

Special Registers Altered:<br />

ACC<br />

Chapter 6. Signal Processing Engine (SPE)<br />

225

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