Power ISA™ Version 2.03 - Power.org

Version 2.03
decimal
SPR 1 Register Privileged Length
spr 5:9 spr 0:4 Name mtspr mfspr (bits)
Cat 2
- This register is not defined for this instruction.
1 Note that the order of the two 5-bit halves of the SPR number is reversed.
2 See Section 1.3.5 of Book I.
3 This register is a hypervisor resource, and can be modified by this instruction
only in hypervisor state (see Chapter 2 of Book III-S).
4 This register is a hypervisor resource, and can be modified by this
instruction only in hypervisor state (see Chapter 2 of Book III-S).
This register is privileged.
5 This register cannot be directly written to. Instead, bits in the register corresponding
to 1 bits in (RS) can be cleared using mtspr SPR,RS.
6 The register can be written by the dcread instruction.
7 The register can be written by the icread instruction.
All SPR numbers that are not shown above and are not implementation-specific
are reserved.
Appendix C. Complete SPR List
739