Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Rotate Left Word Immediate
EVX-form
evrlwi
RT,RA,UI
4 RT RA UI 554
0 6 11 16 21 31
n UI
RT 0:31 ROTL((RA) 0:31 , n)
RT 32:63 ROTL((RA) 32:63 , n)
Both the high and low elements of RA are rotated left
by an amount specified by UI.
Special Registers Altered:
None
Vector Round Word
evrndw
RT,RA
4 RT RA /// 524
RT 0:31 ((RA) 0:31 +0x00008000) & 0xFFFF0000
RT 32:63 ((RA) 32:63 +0x00008000) & 0xFFFF0000
EVX-form
0 6 11 16 21 31
The 32-bit elements of RA are rounded into 16 bits. The
result is placed in RT. The resulting 16 bits are placed
in the most significant 16 bits of each element of RT,
zeroing out the low-order 16 bits of each element.
Special Registers Altered:
None
Vector Select
EVS-form
evsel
RT,RA,RB,BFA
4 RT RA RB 79 BFA
0 6 11 16 21 29 31
ch CR BFA×4
cl CR BFA×4+1
if (ch = 1) then RT 0:31 (RA) 0:31
else RT 0:31 (RB) 0:31
if (cl = 1) then RT 32:63 (RA) 32:63
else RT 32:63 (RB) 32:63
If the most significant bit in the BFA field of CR is set to
1, the high-order element of RA is placed in the
high-order element of RT; otherwise, the high-order element
of RB is placed into the high-order element of RT.
If the next most significant bit in the BFA field of CR is
set to 1, the low-order element of RA is placed in the
low-order element of RT, otherwise, the low-order element
of RB is placed into the low-order element of RT.
Special Registers Altered:
None
Chapter 6. Signal Processing Engine (SPE)
241