Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Load Double Word into Double
Word
EVX-form
Vector Load Double Word into Double
Word Indexed
EVX-form
evldd
RT,D(RA)
evlddx
RT,RA,RB
4 RT RA UI 769
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + EXTZ(UI×8)
RT MEM(EA, 8)
D in the instruction mnemonic is UI × 8. The doubleword
addressed by EA is loaded from memory and
placed in RT.
Special Registers Altered:
None
4 RT RA RB 768
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + (RB)
RT MEM(EA, 8)
The doubleword addressed by EA is loaded from memory
and placed in RT.
Special Registers Altered:
None
Vector Load Double into Four Halfwords
EVX-form
Vector Load Double into Four Halfwords
Indexed
EVX-form
evldh
RT,D(RA)
evldhx
RT,RA,RB
4 RT RA UI 773
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + EXTZ(UI×8)
RT 0:15 MEM(EA, 2)
RT 16:31 MEM(EA+2,2)
RT 32:47 MEM(EA+4,2)
RT 48:63 MEM(EA+6,2)
D in the instruction mnemonic is UI × 8. The doubleword
addressed by EA is loaded from memory and
placed in RT.
Special Registers Altered:
None
4 RT RA RB 772
0 6 11 16 21 31
if (RA = 0) then b 0
else b (RA)
EA b + (RB)
RT 0:15 MEM(EA, 2)
RT 16:31 MEM(EA+2,2)
RT 32:47 MEM(EA+4,2)
RT 48:63 MEM(EA+6,2)
The doubleword addressed by EA is loaded from memory
and placed in RT.
Special Registers Altered:
None
208
Power ISA -- Book I