Power ISA™ Version 2.03 - Power.org

Version 2.03
4.3 Instruction Fetch
The effective address for an instruction fetch is processed
under control of MSR IS . The Address Translation
mechanism is described beginning in
Section 4.7.2.
4.3.1 Implicit Branch
Explicitly altering certain MSR bits (using mtmsr), or
explicitly altering TLB entries, certain System Registers
and possibly other implementation-dependent registers,
may have the side effect of changing the
addresses, effective or real, from which the current
instruction stream is being fetched. This side effect is
called an implicit branch. For example, an mtmsr
instruction that changes the value of MSR CM may
change the real address from which the current instruction
stream is being fetched. The MSR bits and System
Registers (excluding implementation-dependent registers)
for which alteration can cause an implicit branch
are indicated as such in Chapter 10. “Synchronization
Requirements for Context Alterations” on page 603.
Implicit branches are not supported by the Power ISA.
If an implicit branch occurs, the results are boundedly
undefined.
4.3.2 Address Wrapping Combined
with Changing MSR Bit CM
If the current instruction is at effective address 2 32 -4
and is an mtmsr instruction that changes the contents
of MSR CM , the effective address of the next sequential
instruction is undefined.
Programming Note
In the case described in the preceding paragraph, if
an interrupt occurs before the next sequential
instruction is executed, the contents of SRR0,
CSRR0, or MCSRR0, as appropriate to the interrupt,
are undefined.
4.4 Data Access
The effective address for a data access is processed
under control of MSR DS . The Address Translation
mechanism is described beginning in Section 4.7.2.
Storage control attributes may also affect instruction
fetch.
4.5 Performing Operations
Out-of-Order
An operation is said to be performed “in-order” if, at the
time that it is performed, it is known to be required by
the sequential execution model. An operation is said to
be performed “out-of-order” if, at the time that it is performed,
it is not known to be required by the sequential
execution model.
Operations are performed out-of-order by the processor
on the expectation that the results will be needed by
an instruction that will be required by the sequential
execution model. Whether the results are really needed
is contingent on everything that might divert the control
flow away from the instruction, such as Branch, Trap,
System Call, and Return From Interrupt instructions,
and interrupts, and on everything that might change the
context in which the instruction is executed.
Typically, the processor performs operations out-oforder
when it has resources that would otherwise be
idle, so the operation incurs little or no cost. If subsequent
events such as branches or interrupts indicate
that the operation would not have been performed in
the sequential execution model, the processor abandons
any results of the operation (except as described
below).
In the remainder of this section, including its subsections,
“Load instruction” includes the Cache Management
and other instructions that are stated in the
instruction descriptions to be “treated as a Load”, and
similarly for “Store instruction”.
A data access that is performed out-of-order may correspond
to an arbitrary Load or Store instruction (e.g., a
Load or Store instruction that is not in the instruction
stream being executed). Similarly, an instruction fetch
that is performed out-of-order may be for an arbitrary
instruction (e.g., the aligned word at an arbitrary location
in instruction storage).
Most operations can be performed out-of-order, as long
as the machine appears to follow the sequential execution
model. Certain out-of-order operations are
restricted, as follows.
Stores
Stores are not performed out-of-order (even if the
Store instructions that caused them were executed
out-of-order).
Accessing Guarded Storage
The restrictions for this case are given in Section
4.8.1.1.
The only permitted side effects of performing an operation
out-of-order are the following.
A Machine Check that could be caused by in-order
execution may occur out-of-order.
Non-Guarded storage locations that could be
fetched into a cache by in-order fetching or execution
of an arbitrary instruction may be fetched outof-order
into that cache.
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Power ISA -- Book III-E