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Version 2.03
ing the ptesync instruction are performed with
respect to that processor or mechanism.
7. There are additional software synchronization
requirements for this instruction in multiprocessor
environments (e.g., it may be necessary to invalidate
one or more TLB entries on all processors in
the multiprocessor system and to be able to determine
that the invalidations have completed and
that all side effects of the invalidations have taken
effect).
Section 5.10 gives examples of using tlbie, Store,
and related instructions to maintain the Page
Table, in both multiprocessor and uniprocessor
environments.
Programming Note
In a multiprocessor system, if software locking
is used to help ensure that the requirements
described in Section 5.10 are satisfied, the
lwsync instruction near the end of the lock
acquisition sequence (see Section B.2.1.1 of
Book II) may naturally provide the context synchronization
that is required before the alteration.
No slbie (or slbia) is needed if the slbmte instruction
replaces a valid SLB entry with a mapping of a
different ESID (e.g., to satisfy an SLB miss). However,
the slbie is needed later if and when the
translation that was contained in the replaced SLB
entry is to be invalidated.
12. The context synchronizing instruction before the
mtspr instruction ensures that the LPIDR is not
altered out-of-order. (Out-of-order alteration of the
LPIDR could permit the requirements described in
Section 5.10.1 to be violated. For the same reason,
such a context synchronizing instruction may
be needed even if the new LPID value is equal to
the old LPID value.)
See also Chapter 2. “Logical Partitioning (LPAR)”
on page 389 regarding moving a processor from
one partition to another.
13. When the RMOR or HRMOR is modified, or the
RMLS, LPES 1 , or RMI fields of the LPCR are modified,
software must invalidate all implementationspecific
lookaside information used in address
translation that depends on values stored in these
registers. All implementations provide a means by
which software can do this.
8. The alteration must not cause an implicit branch in
effective address space. Thus, when changing
MSR SF from 1 to 0, the mtmsrd instruction must
have an effective address that is less than 2 32 - 4.
Furthermore, when changing MSR SF from 0 to 1,
the mtmsrd instruction must not be at effective
address 2 32 - 4 (see Section 5.3.2 on page 408).
9. The alteration must not cause an implicit branch in
real address space. Thus the real address of the
context-altering instruction and of each subsequent
instruction, up to and including the next context
synchronizing instruction, must be
independent of whether the alteration has taken
effect.
10. The elapsed time between the contents of the Decrementer
or Hypervisor Decrementer becoming
negative and the signaling of the corresponding
exception is not defined.
11. If an slbmte instruction alters the mapping, or
associated attributes, of a currently mapped ESID,
the slbmte must be preceded by an slbie (or
slbia) instruction that invalidates the existing
translation. This applies even if the corresponding
entry is no longer in the SLB (the translation may
still be in implementation-specific address translation
lookaside information). No software synchronization
is needed between the slbie and the
slbmte, regardless of whether the index of the
SLB entry (if any) containing the current translation
is the same as the SLB index specified by the slbmte.
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Power ISA -- Book III-S