Power ISA™ Version 2.03 - Power.org

Version 2.03
SX Supervisor State Execute Enable See Section
4.7.4.1.
0 Instruction fetch and execution is not permitted
from this page while MSR PR =0 and will
cause an Execute Access Control exception
type Instruction Storage interrupt.
1 Instruction fetch and execution is permitted
from this page while MSR PR =1.
UW User State Write Enable See Section
4.7.4.2.
0 Store operations, including dcba dcbz, and
dcbzep are not permitted to this page when
MSR PR =1 and will cause a Write Access
Control exception. Except as noted in
Table 3 on page 528, a Write Access Control
exception will cause a Data Storage interrupt.
1 Store operations, including dcba, dcbz, and
dcbzep are permitted to this page when
MSR PR =1.
SW Supervisor State Write Enable See Section
4.7.4.2.
0 Store operations, including dcba, dcbi,
dcbz, and dcbzep are not permitted to this
page when MSR PR =0. Store operations,
including dcbi, dcbz, and dcbzep, will
cause a Write Access Control exception.
Except as noted in Table 3 on page 528, a
Write Access Control exception will cause a
Data Storage interrupt.
1 Store operations, including dcba, dcbi,
dcbz, and dcbzep, are permitted to this
page when MSR PR =0.
UR User State Read Enable See Section
4.7.4.3.
0 Load operations (including load-class Cache
Management instructions) are not permitted
from this page when MSR PR =1 and will
cause a Read Access Control exception.
Except as noted in Table 3 on page 528, a
Read Access Control exception will cause a
Data Storage interrupt.
1 Load operations (including load-class Cache
Management instructions) are permitted
from this page when MSR PR =1.
SR Supervisor State Read Enable See Section
4.7.4.3.
0 Load operations (including load-class Cache
Management instructions) are not permitted
from this page when MSR PR =0 and will
cause a Read Access Control exception.
Except as noted in Table 3 on page 528, a
Read Access Control exception will cause a
Data Storage interrupt.
1 Load operations (including load-class Cache
Management instructions) are permitted
from this page when MSR PR =0.
4.7.2 Page Identification
Instruction effective addresses are generated for
sequential instruction fetches and for addresses that
correspond to a change in program flow (branches,
interrupts). Data effective addresses are generated by
Load, Store, and Cache Management instructions. TLB
Management instructions generate effective addresses
to determine the presence of or to invalidate a specific
TLB entry associated with that address.
The Valid (V) bit, Effective Page Number (EPN) field,
Translation Space Identifier (TS) bit, Page Size (SIZE)
field, and Translation ID (TID) field of a particular TLB
entry identify the page associated with that TLB entry.
Except as noted, all comparisons must succeed to validate
this entry for subsequent translation and access
control processing. Failure to locate a matching TLB
entry based on this criteria for instruction fetches will
result in an Instruction TLB Miss exception type Instruction
TLB Error interrupt. Failure to locate a matching
TLB entry based on this criteria for data storage
accesses will result in a Data TLB Miss exception
which may result in a Data TLB Error interrupt. Figure 8
on page 524 illustrates the criteria for a virtual address
to match a specific TLB entry.
There are two address spaces, one typically associated
with interrupt-related storage accesses and one typically
associated with non-interrupt-related storage
accesses. There are two bits in the Machine State Register,
the Instruction Address Space bit (IS) and the
Data Address Space bit (DS), that control which
address space instruction and data storage accesses,
respectively, are performed in, and a bit in the TLB
entry (TS) that specifies which address space that TLB
entry is associated with.
Load, Store, Cache Management, Branch, tlbsx, and
tlbivax instructions and next-sequential-instruction
fetches produce a 64-bit effective address. The virtual
address space is extended from this 64-bit effective
address space by prepending a one-bit address space
identifier and a process identifier. For instruction
fetches, the address space identifier is provided by
MSR IS and the process identifier is provided by the
contents of the Process ID Register. For data storage
accesses, the address space identifier is provided by
the MSR DS and the process identifier is provided by the
contents of the Process ID Register. For tlbsx, and
tlbivax instructions, the address space identifier and
the process identifier are provided by implementationdependent
sources.
This virtual address is used to locate the associated
entry in the TLB. The address space identifier, the process
identifier, and the effective address of the storage
access are compared to the Translation Address Space
bit (TS), the Translation ID field (TID), and the value in
the Effective Page Number field (EPN), respectively, of
each TLB entry.
Chapter 4. Storage Control
523