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Version 2.03
Check interrupts) will occur as a result of those
instructions.
5.5 Interrupt Processing
Associated with each kind of interrupt is an interrupt
vector, that is the address of the initial instruction that is
executed when the corresponding interrupt occurs.
Interrupt processing consists of saving a small part of
the processor’s state in certain registers, identifying the
cause of the interrupt in another register, and continuing
execution at the corresponding interrupt vector
location. When an exception exists that will cause an
interrupt to be generated and it has been determined
that the interrupt can be taken, the following actions are
performed, in order:
1. SRR0, DSRR0 [Category: Embedded.Enhanced
Debug], MCSRR0, or CSRR0 is loaded with an
instruction address that depends on the interrupt;
see the specific interrupt description for details.
2. The ESR is loaded with information specific to the
exception. Note that many interrupts can only be
caused by a single kind of exception event, and
thus do not need nor use an ESR setting to indicate
to the cause of the interrupt was.
3. SRR1, DSRR1 [Category: Embedded.Enhanced
Debug], or MCSRR1, or CSRR1 is loaded with a
copy of the contents of the MSR.
4. The MSR is updated as described below. The new
values take effect beginning with the first instruction
following the interrupt. MSR bits of particular
interest are the following.
MSR WE,EE,PR,FP,FE0,FE1,IS,DS are set to 0 by
all interrupts.
MSR ME is set to 0 by Machine Check interrupts
and left unchanged by all other interrupts.
MSR CE is set to 0 by critical class interrupts,
Debug interrupts, and Machine Check interrupts,
and is left unchanged by all other interrupts.
MSR DE is set to 0 by critical class interrupts
unless Category E.ED is supported, by Debug
interrupts, and by Machine Check interrupts,
and is left unchanged by all other interrupts.
MSR CM is set to MSR ICM .
Other supported MSR bits are left unchanged
by all interrupts.
See Section 2.2.1 for more detail on the definition
of the MSR.
5. Instruction fetching and execution resumes, using
the new MSR value, at a location specific to the
interrupt. The location is
IVPR 0:47 || IVORi 48:59 || 0b0000
where IVPR is the Interrupt Vector Prefix Register
and IVORi is the Interrupt Vector Offset Register
for that interrupt (see Figure 13 on page 546). The
contents of the Interrupt Vector Prefix Register and
Interrupt Vector Offset Registers are indeterminate
upon power-on reset, and must be initialized by
system software using the mtspr instruction.
Interrupts may not clear reservations obtained with
Load and Reserve instructions. The operating system
should do so at appropriate points, such as at process
switch.
At the end of an interrupt handling routine, execution of
an rfi, rfdi [Category: Embedded.Enhanced Debug],
rfmci, or rfci causes the MSR to be restored from the
contents of SRR1, DSRR1 [Category: Embedded.Enhanced
Debug], MCSRR1, or CSRR1, and
instruction execution to resume at the address contained
in SRR0, DSRR0 [Category: Embedded.Enhanced
Debug], MCSRR0, or CSRR0,
respectively.
Programming Note
In general, at process switch, due to possible process
interlocks and possible data availability
requirements, the operating system needs to consider
executing the following.
stwcx. or stdcx., to clear the reservation if
one is outstanding, to ensure that a lwarx or
ldarx in the “old” process is not paired with a
stwcx. or stdcx. in the “new” process.
msync, to ensure that all storage operations of
an interrupted process are complete with
respect to other processors before that process
begins executing on another processor.
isync, rfi, rfdi [Category: Embedded.Enhanced
Debug], rfmci, or rfci to ensure
that the instructions in the “new” process execute
in the “new” context.
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Power ISA -- Book III-E