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restore machine state when an rfid instruction is executed.
SRR0 //
0 62 63
SRR1
0 63
Figure 30. Save/Restore Registers
SRR1 bits may be treated as reserved in a given implementation
if they correspond to MSR bits that are
reserved or are treated as reserved in that implementation
or, for SRR1 bits in the range 33:36 and 42:47,
they are specified as being set either to 0 or to an
undefined value for all interrupts that set SRR1 (including
implementation-dependent setting, e.g. by the
Machine Check interrupt or by implementation-specific
interrupts).
6.2.2 Hypervisor Machine Status
Save/Restore Registers
When a Hypervisor Decrementer interrupt occurs, the
state of the machine is saved in the Hypervisor
Machine Status Save/Restore registers (HSRR0 and
HSRR1). The contents of these registers are used to
restore machine state when an hrfid instruction is executed.
HSRR0 //
0 62 63
HSRR1
0 63
Figure 31. Hypervisor Save/Restore Registers
6.2.3 Data Address Register
The Data Address Register (DAR) is a 64-bit register
that is set by the Machine Check, Data Storage, Data
Segment, and Alignment interrupts; see Sections 6.5.2,
6.5.3, 6.5.4, and 6.5.8. In general, when one of these
interrupts occurs the DAR is set to an effective address
associated with the storage access that caused the
interrupt, with the high-order 32 bits of the DAR set to 0
if the interrupt occurs in 32-bit mode.
DAR
0 63
Figure 32. Data Address Register
6.2.4 Data Storage Interrupt
Status Register
The Data Storage Interrupt Status Register (DSISR) is
a 32-bit register that is set by the Machine Check, Data
Storage, Data Segment, and Alignment interrupts; see
Sections 6.5.2, 6.5.3, 6.5.4, and 6.5.8. In general, when
one of these interrupts occurs the DSISR is set to indicate
the cause of the interrupt.
DSISR
32 63
Figure 33. Data Storage Interrupt Status Register
DSISR bits may be treated as reserved in a given
implementation if they are specified as being set either
to 0 or to an undefined value for all interrupts that set
the DSISR (including implementation-dependent setting,
e.g. by the Machine Check interrupt or by implementation-specific
interrupts).
HSRR1 bits may be treated as reserved in a given
implementation if they correspond to MSR bits that are
reserved or are treated as reserved in that implementation
or, for HSRR1 bits in the range 33:36 and 42:47,
they are specified as being set either to 0 or to an
undefined value for all interrupts that set HSRR1
(including implementation-dependent setting, e.g. by
implementation-specific interrupts).
The HSRR0 and HSRR1 are hypervisor resources; see
Chapter 2.
Programming Note
Execution of some instructions, and fetching
instructions when MSR IR =1, may have the side
effect of modifying HSRR0 and HSRR1; see Section
6.4.4.
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Power ISA -- Book III-S