Power ISA™ Version 2.03 - Power.org

Version 2.03
40:41 Data Address Compare 1/2 Mode
(DAC12M)
00 Exact address compare
DAC1 debug events can occur only if the
address of the data storage access is equal
to the value specified in DAC1.
DAC2 debug events can occur only if the
address of the data storage access is equal
to the value specified in DAC2.
01 Address bit match
DAC1 and DAC2 debug events can occur
only if the address of the data storage
access, ANDed with the contents of DAC2
are equal to the contents of DAC1, also
ANDed with the contents of DAC2.
If DAC1US≠DAC2US or
DAC1ER≠DAC2ER, results are boundedly
undefined.
10 Inclusive address range compare
DAC1 and DAC2 debug events can occur
only if the address of the data storage
access is greater than or equal to the value
specified in DAC1 and less than the value
specified in DAC2.
If DAC1US ≠ DAC2US or DAC1ER ≠
DAC2ER, results are boundedly undefined.
11 Exclusive address range compare
DAC1 and DAC2 debug events can occur
only if the address of the data storage
access is less than the value specified in
DAC1 or is greater than or equal to the
value specified in DAC2.
If DAC1US ≠ DAC2US or DAC1ER ≠
DAC2ER, results are boundedly undefined.
42:43 Reserved
44:45 Data Value Compare 1 Mode (DVC1M)
00 DAC1 debug events can occur
01 DAC1 debug events can occur only when
all bytes specified in DBCR2 DVC1BE in the
data value of the data storage access
match their corresponding bytes in DVC1
10 DAC1 debug events can occur only when
at least one of the bytes specified in
DBCR2 DVC1BE in the data value of the
data storage access matches its corresponding
byte in DVC1
11 DAC1 debug events can occur only when
all bytes specified in DBCR2 DVC1BE within
at least one of the halfwords of the data
value of the data storage access matches
their corresponding bytes in DVC1
46:47 Data Value Compare 2 Mode (DVC2M)
00 DAC2 debug events can occur
01 DAC2 debug events can occur only when
all bytes specified in DBCR2 DVC2BE in the
data value of the data storage access
match their corresponding bytes in DVC2
10 DAC2 debug events can occur only when
at least one of the bytes specified in
DBCR2 DVC2BE in the data value of the
data storage access matches its corresponding
byte in DVC2
11 DAC2 debug events can occur only when
all bytes specified in DBCR2 DVC2BE within
at least one of the halfwords of the data
value of the data storage access matches
their corresponding bytes in DVC2
48:55 Data Value Compare 1 Byte Enables
(DVC1BE)
Specifies which bytes in the aligned data
value being read or written by the storage
access are compared to the corresponding
bytes in DVC1.
56:63 Data Value Compare 2 Byte Enables
(DVC2BE)
Specifies which bytes in the aligned data
value being read or written by the storage
access are compared to the corresponding
bytes in DVC2
8.5.2 Debug Status Register
The Debug Status Register (DBSR) is a 32-bit register
and contains status on debug events and the most
recent processor reset.
The DBSR is set via hardware, and read and cleared
via software. The contents of the DBSR can be read
into bits 32:63 of a register RT using the mfspr instruction,
setting bits 0:31 of RT to zero. Bits in the DBSR
can be cleared using the mtspr instruction. Clearing is
done by writing bits 32:63 of a register to the DBSR
with a 1 in any bit position that is to be cleared and 0 in
all other bit positions. The write-data to the DBSR is not
direct data, but a mask. A 1 causes the bit to be
cleared, and a 0 has no effect.
The bit definitions for the DBSR are shown below:
Bit(s) Description
32 Imprecise Debug Event (IDE)
Set to 1 if MSR DE =0 and a debug event
causes its respective Debug Status Register
bit to be set to 1.
33 Unconditional Debug Event (UDE)
Set to 1 if an Unconditional debug event
occurred. See Section 8.4.8.
Chapter 8. Debug Facilities
595