Power ISA™ Version 2.03 - Power.org

Version 2.03
Move To Special Purpose Register
XFX-form
mtspr
SPR,RS
31 RS spr 467 /
0 6 11 21 31
n spr 5:9 || spr 0:4
if length(SPR(n)) = 64 then
SPR(n) (RS)
else
SPR(n) (RS) 32:63
The SPR field denotes a Special Purpose Register,
encoded as shown in Figure 13. The contents of register
RS are placed into the designated Special Purpose
Register. For Special Purpose Registers that are 32 bits
long, the low-order 32 bits of RS are placed into the
SPR.
For this instruction, SPRs TBL and TBU are treated as
separate 32-bit registers; setting one leaves the other
unaltered.
spr 0 =1 if and only if writing the register is privileged.
Execution of this instruction specifying a defined and
privileged register when MSR PR =1 causes a Privileged
Instruction type Program interrupt. Execution of this
instruction specifying a hypervisor resource when
MSR HV PR = 0b00 either has no effect or causes a Privileged
Instruction type Program interrupt (Chapter 2.,
“Logical Partitioning (LPAR)”, on page 389).
Execution of this instruction specifying an SPR number
that is not defined for the implementation causes either
an Illegal Instruction type Program interrupt or one of
the following.
if spr 0 =0: boundedly undefined results
if spr 0 =1:
- if MSR PR =1: Privileged Instruction type Program
interrupt
- if MSR PR =0 and MSR HV =0: boundedly undefined
results
- if MSR PR =0 and MSR HV =1: undefined results
If the SPR number is set to a value that is shown in
Figure 13 but corresponds to an optional Special Purpose
Register that is not provided by the implementation,
the effect of executing this instruction is the same
as if the SPR number were reserved.
Special Registers Altered:
See Figure 13
Move From Special Purpose Register
XFX-form
mfspr
RT,SPR
31 RT spr 339 /
0 6 11 21 31
n spr 5:9 || spr 0:4
if length(SPR(n)) = 64 then
RT SPR(n)
else
RT 32 0 || SPR(n)
The SPR field denotes a Special Purpose Register,
encoded as shown in Figure 13. The contents of the
designated Special Purpose Register are placed into
register RT. For Special Purpose Registers that are 32
bits long, the low-order 32 bits of RT receive the contents
of the Special Purpose Register and the highorder
32 bits of RT are set to zero.
spr 0 =1 if and only if reading the register is privileged.
Execution of this instruction specifying a defined and
privileged register when MSR PR =1 causes a Privileged
Instruction type Program interrupt.
Execution of this instruction specifying an SPR number
that is not defined for the implementation causes either
an Illegal Instruction type Program interrupt or one of
the following.
if spr 0 =0: boundedly undefined results
if spr 0 =1:
- if MSR PR =1: Privileged Instruction type Program
interrupt
- if MSR PR =0: boundedly undefined results
If the SPR field contains a value that is shown in
Figure 13 but corresponds to an optional Special Purpose
Register that is not provided by the implementation,
the effect of executing this instruction is the same
as if the SPR number were reserved.
Special Registers Altered:
None
Note
See the Notes that appear with mtspr.
Programming Note
For a discussion of software synchronization
requirements when altering certain Special Purpose
Registers, see Chapter 10. “Synchronization
Requirements for Context Alterations” on
page 467.
Chapter 4. Fixed-Point Processor
403