Power ISA™ Version 2.03 - Power.org

Version 2.03
Load Halfword Algebraic with Update
D8-form
Load Halfword and Zero with Update
D8-form
e_lhau
RT,D8(RA)
e_lhzu
RT,D8(RA)
06 RT RA 03 D8
0 6 11 16 24 31
EA (RA) + EXTS(D8)
RT EXTS(MEM(EA, 2))
RA EA
Let the effective address (EA) be the sum (RA) + D8.
The halfword in storage addressed by EA is loaded into
RT 48:63 . RT 0:47 are filled with a copy of bit 0 of the
loaded halfword.
EA is placed into RA.
If RA=0 or RA=RT, the instruction form is invalid.
Special Registers Altered:
None
06 RT RA 01 D8
0 6 11 16 24 31
EA (RA) + EXTS(D8)
RT 48 0 || MEM(EA, 2))
RA EA
Let the effective address (EA) be the sum (RA) + D8.
The halfword in storage addressed by EA is loaded into
RT 48:63 . RT 0:47 are set to 0.
EA is placed into register RA.
If RA=0 or RA=RT, the instruction form is invalid.
Special Registers Altered:
None
Load Word and Zero
D-form
Load Word and Zero Short FormSD4-form
e_lwz
RT,D(RA)
se_lwz
RZ,SD4(RX)
20 RT RA D
0 6 11 16 31
if RA = 0 then b 0
else
b (RA)
EA b + EXTS(D)
RT 32 0 || MEM(EA, 4)
Let the effective address (EA) be the sum (RA|0) + D.
The word in storage addressed by EA is loaded into
RT 32:63 . RT 0:31 are set to 0.
Special Registers Altered:
None
12 SD4 RZ RX
0 4 8 12 15
EA (RX)+ ( 58 0 || SD4 || 2 0)
RZ 32 0 || MEM(EA, 2)
Let the effective address (EA) be the sum (RX) + (SD4
|| 00). The word in storage addressed by EA is loaded
into RZ 32:63 . RZ 0:31 are set to 0.
Special Registers Altered:
None
Chapter 5. Fixed-Point Instructions
665