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Load or Store instruction that causes an atomic
access
If any portion of the storage operand has been
accessed, the instruction completes before the
interrupt occurs if any of the following exceptions is
pending.
External, Decrementer, Critical Input, Machine
Check, Fixed-Interval Timer, Watchdog Timer,
Debug, or Imprecise mode Floating-Point or
Auxiliary Processor Enabled
Load or Store instruction that causes an Alignment
exception, a Data TLB Error exception, or that
causes a Data Storage exception.
The portion of the storage operand that is in Caching
Inhibited and Guarded storage is not accessed.
4.8.1.1 Out-of-Order Accesses to
Guarded Storage
In general, Guarded storage is not accessed out-oforder.
The only exceptions to this rule are the following.
Load Instruction
If a copy of any byte of the storage operand is in a
cache then that byte may be accessed in the cache or
in main storage.
4.8.2 User-Definable
User-definable storage control attributes control userdefinable
and implementation-dependent behavior of
the storage system. These bits are both implementation-dependent
and system-dependent in their effect.
They may be used in any combination and also in combination
with the other storage attribute bits.
4.8.3 Storage Control Bits
Storage control attributes are specified on a per-page
basis. These attributes are specified in storage control
bits in the TLB entries. The interpretation of their values
is given in Figure 11.
Bit
W 1
I
M 2
G
E 3
Storage Control Attribute
0 - not Write Through Required
1 - Write Through Required
0 - not Caching Inhibited
1 - Caching Inhibited
0 - not Memory Coherence Required
1 - Memory Coherence Required
0 - not Guarded
1 - Guarded
0 - Big-Endian
1 - Little-Endian
User-Definable
U0-U3 4
VLE 5 0 - non Variable Length Encoding (VLE).
1 - VLE
1 Support for the 1 value of the W bit is optional.
Implementations that do not support the 1 value
treat the bit as reserved and assume its value to
be 0.
2 Support of the 1 value is optional for implementations
that do not support multiprocessing, implementations
that do not support this storage
attribute assume the value of the bit to be 0, and
setting M=1 in a TLB entry will have no effect.
3 [Category: Embedded.Little-Endian]
4 Support for these attributes is optional.
5 [Category: VLE]
Figure 11. Storage control bits
In Section 4.8.3.1 and 4.8.3.2, “access” includes
accesses that are performed out-of-order.
Programming Note
In a uniprocessor system in which only the processor
has caches, correct coherent execution does
not require the processor to access storage as
Memory Coherence Required, and accessing storage
as not Memory Coherence Required may give
better performance.
4.8.3.1 Storage Control Bit Restrictions
All combinations of W, I, M, G, and E values are permitted
except those for which both W and I are 1.
Programming Note
If an application program requests both the Write
Through Required and the Caching Inhibited
attributes for a given storage location, the operating
system should set the I bit to 1 and the W bit to 0.
At any given time, the value of the I bit must be the
same for all accesses to a given real page.
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Power ISA -- Book III-E