Power ISA™ Version 2.03 - Power.org

Version 2.03
For an X-form Load or Store, it is acceptable for the
processor to set the DSISR to the same value that
would have resulted if the corresponding D- or DS-form
instruction had caused the interrupt. Similarly, for a D-
or DS-form Load or Store, it is acceptable for the processor
to set the DSISR to the value that would have
resulted for the corresponding X-form instruction. For
example, an unaligned lwax (that crosses a protection
boundary) would normally, following the description
above, cause the DSISR to be set to binary:
000000000000 00 0 01 0 0101 ttttt ?????
where “ttttt” denotes the RT field, and “?????” denotes
an undefined 5-bit value. However, it is acceptable if it
causes the DSISR to be set as for lwa, which is
000000000000 10 0 00 0 1101 ttttt ?????
If there is no corresponding alternative form instruction
(e.g., for lwaux), the value described above is set in
the DSISR.
The instruction pairs that may use the same DSISR
value are.
lhz/lhzx lhzu/lhzux lha/lhax lhau/lhaux
lwz/lwzx lwzu/lwzux lwa/lwax
ld/ldx ldu/ldux
lsth/sthx sthu/sthux stw/stwx stwu/stwux
std/stdx stdu/stdux
lfs/lfsx lfsu/lfsux lfd/lfdx lfdu/lfdux
stfs/stfsx stfsu/stfsux stfd/stfdx stfdu/stfdux
Execution resumes at effective address
0x0000_0000_0000_0600.
Programming Note
The architecture does not support the use of an
unaligned effective address by lwarx, ldarx,
stwcx., stdcx., eciwx, and ecowx. If an Alignment
interrupt occurs because one of these instructions
specifies an unaligned effective address, the
Alignment interrupt handler must not attempt to
simulate the instruction, but instead should treat
the instruction as a programming error.
6.5.9 Program Interrupt
A Program interrupt occurs when no higher priority
exception exists and one of the following exceptions
arises during execution of an instruction:
Floating-Point Enabled Exception
A Floating-Point Enabled Exception type Program
interrupt is generated when the value of the
expression
(MSR FE0 | MSR FE1 ) & FPSCR FEX
is 1. FPSCR FEX is set to 1 by the execution of a
floating-point instruction that causes an enabled
exception, including the case of a Move To FPSCR
instruction that causes an exception bit and the
corresponding enable bit both to be 1.
Illegal Instruction
An Illegal Instruction type Program interrupt is generated
when execution is attempted of an illegal
instruction, or of a reserved instruction or an
instruction that is not provided by the implementation.
An Illegal Instruction type Program interrupt may
be generated when execution is attempted of any
of the following kinds of instruction.
an instruction that is in invalid form
an lswx instruction for which RA or RB is in
the range of registers to be loaded
an mtspr or mfspr instruction with an SPR
field that does not contain one of the defined
values
Privileged Instruction
The following applies if the instruction is executed
when MSR PR = 1.
A Privileged Instruction type Program interrupt
is generated when execution is attempted of a
privileged instruction, or of an mtspr or mfspr
instruction with an SPR field that contains one
of the defined values having spr 0 =1. It may be
generated when execution is attempted of an
mtspr or mfspr instruction with an SPR field
that does not contain one of the defined values
but has spr 0 =1.
The following applies if the instruction is executed
when MSR HV PR = 0b00.
A Privileged Instruction type Program interrupt
may be generated when execution is
attempted of an mtspr instruction with an
SPR field that designates a hypervisor
resource, or when execution of a tlbie, tlbiel,
tlbia, or tlbsync instruction is attempted.
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Power ISA -- Book III-S