Power ISA™ Version 2.03 - Power.org

Version 2.03
3.3 Synchronization Instructions
The synchronization instructions are used to ensure
that certain instructions have completed before other
instructions are initiated, or to control storage access
ordering, or to support debug operations.
3.3.1 Instruction Synchronize
Instruction
Instruction Synchronize XL-form
isync
19 /// /// /// 150 /
0 6 11 16 21 31
Executing an isync instruction ensures that all instructions
preceding the isync instruction have completed
before the isync instruction completes, and that no
subsequent instructions are initiated until after the
isync instruction completes. It also ensures that all
instruction cache block invalidations caused by icbi
instructions preceding the isync instruction have been
performed with respect to the processor executing the
isync instruction, and then causes any prefetched
instructions to be discarded.
Except as described in the preceding sentence, the
isync instruction may complete before storage
accesses associated with instructions preceding the
isync instruction have been performed.
This instruction is context synchronizing (see Book III).
Special Registers Altered:
None
3.3.2 Load and Reserve and Store
Conditional Instructions
The Load And Reserve and Store Conditional instructions
can be used to construct a sequence of instructions
that appears to perform an atomic update
operation on an aligned storage location. See
Section 1.7.3, “Atomic Update” for additional information
about these instructions.
The Load And Reserve and Store Conditional instructions
are fixed-point Storage Access instructions; see
Section 3.3.1, “Fixed-Point Storage Access Instructions”,
in Book I.
The storage location specified by the Load And
Reserve and Store Conditional instructions must be in
storage that is Memory Coherence Required if the location
may be modified by other processors or mechanisms.
If the specified location is in storage that is Write
Through Required or Caching Inhibited, the system
data storage error handler or the system alignment
error handler is invoked for the Server environment and
may be invoked for the Embedded environment.
Programming Note
The Memory Coherence Required attribute on
other processors and mechanisms ensures that
their stores to the reservation granule will cause
the reservation created by the Load And Reserve
instruction to be lost.
Programming Note
Because the Load And Reserve and Store Conditional
instructions have implementation dependencies
(e.g., the granularity at which reservations are
managed), they must be used with care. The operating
system should provide system library programs
that use these instructions to implement the
high-level synchronization functions (Test and Set,
Compare and Swap, locking, etc.; see Appendix B)
that are needed by application programs. Application
programs should use these library programs,
rather than use the Load And Reserve and Store
Conditional instructions directly.
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Power ISA -- Book II