Power ISA™ Version 2.03 - Power.org

Version 2.03
6. The precision of the Floating-point Enabled Exception
type Program interrupt is controlled by the
MSR FE0,FE1 bits. When MSR FE0,FE1 =0b01 or
0b10, the interrupt may be imprecise. When such
a Program interrupt is taken, if the address saved
in SRR0 is not the address of the instruction that
caused the exception (i.e. the instruction that
caused FPSCR FEX to be set to 1), ESR PIE is set to
1. When MSR FE0,FE1 =0b11, the interrupt is precise.
When MSR FE0,FE1 =0b00, the interrupt is
masked, and the interrupt will subsequently occur
imprecisely if and when Floating-point Enabled
Exception type Program interrupts are enabled by
setting either or both of MSR FE0,FE1 , and will also
cause ESR PIE to be set to 1. See Section 5.6.7.
Also, exception status on the exact cause is available
in the Floating-Point Status and Control Register
(see Section 4.2.2 and Section 4.4 of Book I).
The precision of the Auxiliary Processor Enabled
Exception type Program interrupt is implementation-dependent.
7. Auxiliary Processor exception status is commonly
provided as part of the implementation.
8. Cache locking and cache locking exceptions are
implementation-dependent.
9. Software must examine the instruction and the
subject TLB entry to determine the exact cause of
the interrupt.
10. If the Embedded.Enhanced Debug category is
enabled, this interrupt is not a critical interrupt.
DSRR0 and DSRR1 are used instead of CSRR0
and CSRR1.
5.6.1 Critical Input Interrupt
A Critical Input interrupt occurs when no higher priority
exception exists (see Section 5.9 on page 569), a Critical
Input exception is presented to the interrupt mechanism,
and MSR CE =1. While the specific definition of a
Critical Input exception is implementation-dependent, it
would typically be caused by the activation of an asynchronous
signal that is part of the system. Also, implementations
may provide an alternative means (in
addition to MSR CE ) for masking the Critical Input interrupt.
CSRR0, CSRR1, and MSR are updated as follows:
CSRR0
Set to the effective address of the next
instruction to be executed.
CSRR1 Set to the contents of the MSR at the time
of the interrupt.
MSR
CM MSR CM is set to MSR ICM .
ME, ICM Unchanged.
DE
Unchanged if category E.ED is supported;
otherwise set to 0
All other defined MSR bits set to 0.
Instruction execution resumes at address IVPR 0:47 ||
IVOR0 48:59 ||0b0000.
Programming Note
Software is responsible for taking any action(s) that
are required by the implementation in order to clear
any Critical Input exception status prior to reenabling
MSR CE in order to avoid another, redundant
Critical Input interrupt.
5.6.2 Machine Check Interrupt
A Machine Check interrupt occurs when no higher priority
exception exists (see Section 5.9 on page 569), a
Machine Check exception is presented to the interrupt
mechanism, and MSR ME =1. The specific cause or
causes of Machine Check exceptions are implementation-dependent,
as are the details of the actions taken
on a Machine Check interrupt.
If the Machine Check Extension is implemented,
MCSRR0, MCSRR1, and MCSR are set, otherwise
CSRR0, CSRR1, and ESR are set. The registers are
updated as follows:
CSRR0/MCSRR0
Set to an instruction address. As closely as
possible, set to the effective address of an
instruction that was executing or about to
be executed when the Machine Check
exception occurred.
CSRR1/MCSRR1
Set to the contents of the MSR at the time
of the interrupt.
MSR
CM MSR CM is set to MSR ICM .
DE
Unchanged if category E.ED is supported;
otherwise set to 0.
All other defined MSR bits set to 0.
ESR/MCSR
Implementation-dependent.
Instruction execution resumes at address IVPR 0:47 ||
IVOR1 48:59 ||0b0000.
Programming Note
If a Machine Check interrupt is caused by an error
in the storage subsystem, the storage subsystem
may return incorrect data, that may be placed into
registers and/or on-chip caches.
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Power ISA -- Book III-E