Power ISA™ Version 2.03 - Power.org

Version 2.03
Instruction or Required Required Notes
Event
Before After
interrupt none none
rfi none none
rfci none none
rfmci none none
rfdi[Category:E.ED] none none
sc none none
mtmsr (CM) none none
mtmsr (ICM) none CSI
mtmsr (UCLE) none none
mtmsr (SPV) none none
mtmsr (WE) -- -- 4
mtmsr (CE) none none 5
mtmsr (EE) none none 5
mtmsr (PR) none CSI
mtmsr (FP) none CSI
mtmsr (DE) none CSI
mtmsr (ME) none CSI 3
mtmsr (FE0) none CSI
mtmsr (FE1) none CSI
mtmsr (IS) none CSI 2
mtspr (DEC) none none 8
mtspr (PID) none CSI 2
mtspr (IVPR) none none
mtspr (DBSR) -- -- 6
mtspr
-- -- 6
(DBCR0,DBCR1)
mtspr
-- -- 6
(IAC1,IAC2,IAC3,
IAC4)
mtspr (IVORi) none none
mtspr (TSR) none none 8
mtspr (TCR) none none 8
tlbivax none CSI, or 1,7
CSI and sync
tlbwe none CSI, or 1,7
CSI and sync
wrtee none none 5
wrteei none none 5
Table 4: Synchronization requirements for instruction
fetch and/or execution
Instruction or Required Required Notes
Event
Before After
interrupt none none
rfi none none
rfci none none
rfmci none none
rfdi[Category:E.ED] none none
sc none none
mtmsr (CM) none CSI
mtmsr (ICM) none none
mtmsr (PR) none CSI
mtmsr (ME) none CSI 3
mtmsr (DS) none CSI
mtspr (PID) CSI CSI
mtspr (DBSR) -- -- 6
mtspr
--- --- 6
(DBCR0,DBCR2)
mtspr
-- -- 6
(DAC1,DAC2,
DVC1,DVC2)
tlbivax CSI CSI, or CSI 1,7
and sync
tlbwe CSI CSI, or CSI 1,7
and sync
Table 5: Synchronization requirements for data access
Notes:
1. There are additional software synchronization
requirements for this instruction in multiprocessor
environments (e.g., it may be necessary to invalidate
one or more TLB entries on all processors in
the multiprocessor system and to be able to determine
that the invalidations have completed and
that all side effects of the invalidations have taken
effect); it is also necessary to execute a tlbsync
instruction.
2. The alteration must not cause an implicit branch in
real address space. Thus the real address of the
context-altering instruction and of each subsequent
instruction, up to and including the next context
synchronizing instruction, must be
independent of whether the alteration has taken
effect.
3. A context synchronizing instruction is required
after altering MSR ME to ensure that the alteration
takes effect for subsequent Machine Check interrupts,
which may not be recoverable and therefore
may not be context synchronizing.
4. Synchronization requirements for changing the
Wait State Enable are implementation-dependent,.
5. The effect of changing MSR EE or MSR CE is immediate.
604
Power ISA -- Book III-E