Power ISA™ Version 2.03 - Power.org

Version 2.03
registers are altered except those set by the
interrupt.
- Otherwise either an Illegal Instruction type
Program interrupt occurs (in which case no
architected registers are altered except those
set by the interrupt) or the results are boundedly
undefined (or possibly undefined, for
mtspr; see Book III).
A.18 Effects of Exceptions on
FPSCR Bits FR and FI
For the following cases, POWER does not specify how
FR and FI are set, while Power ISA preserves them for
Invalid Operation Exception caused by a Compare
instruction, sets FI to 1 and FR to an undefined value
for disabled Overflow Exception, and clears them otherwise.
Invalid Operation Exception (enabled or disabled)
Zero Divide Exception (enabled or disabled)
Disabled Overflow Exception
A.19 Store Floating-Point Single
Instructions
There are several respects in which Power ISA is
incompatible with POWER for Store Floating-Point Single
instructions.
POWER uses FPSCR UE to help determine
whether denormalization should be done, while
Power ISA does not. Using FPSCR UE is in fact
incorrect: if FPSCR UE =1 and a denormalized single-precision
number is copied from one storage
location to another by means of lfs followed by
stfs, the two “copies” may not be the same.
For an operand having an exponent that is less
than 874 (unbiased exponent less than -149),
POWER stores a zero (if FPSCR UE =0) while
Power ISA stores an undefined value.
A.20 Move From FPSCR
POWER defines the high-order 32 bits of the result of
mffs to be 0xFFFF_FFFF, while Power ISA specifies
that they are undefined.
A.21 Zeroing Bytes in the Data
Cache
The dclz instruction of POWER and the dcbz instruction
of Power ISA have the same opcode. However, the
functions differ in the following respects.
dclz clears a line while dcbz clears a block.
dclz saves the EA in RA (if RA≠0) while dcbz does
not.
dclz is privileged while dcbz is not.
A.22 Synchronization
The Synchronize instruction (called dcs in POWER)
and the isync instruction (called ics in POWER) cause
more pervasive synchronization in Power ISA than in
POWER. However, unlike dcs, Synchronize does not
wait until data cache block writes caused by preceding
instructions have been performed in main storage.
Also, Synchronize has an L field while dcs does not,
and some uses of the instruction by the operating system
require L=2. (The L field corresponds to
reserved bits in dcs and hence is expected to be zero
in POWER programs; see Section A.3.)
A.23 Move To Machine State
Register Instruction
The mtmsr instruction has an L field in Power ISA but
not in POWER. The function of the variant of mtmsr
with L=1 differs from the function of the instruction in
the POWER architecture in the following ways.
In Power ISA, this variant of mtmsr modifies only
the EE and RI bits of the MSR, while in the
POWER mtmsr modifies all bits of the MSR.
This variant of mtmsr is execution synchronizing
in Power ISA but is context synchronizing in
POWER. (The POWER architecture lacks Power
ISA’s distinction between execution synchronization
and context synchronization. The statement in
the POWER architecture specification that mtmsr
is “synchronizing” is equivalent to stating that the
instruction is context synchronizing.)
Also, mtmsr is optional in Power ISA but required in
POWER.
A.24 Direct-Store Segments
POWER’s direct-store segments are not supported in
Power ISA.
A.25 Segment Register
Manipulation Instructions
The definitions of the four Segment Register Manipulation
instructions mtsr, mtsrin, mfsr, and mfsrin differ
in two respects between POWER and Power ISA.
Instructions similar to mtsrin and mfsrin are called
mtsri and mfsri in POWER.
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Power ISA -- Book Appendices