Power ISA™ Version 2.03 - Power.org

Version 2.03
Return From Machine-Check Interrupt
XL-form
rfmci
19 /// /// /// 38 /
0 6 11 16 21 31
MSR MCSRR1
NIA iea MCSRR0 0:61 || 0b00
The rfmci instruction is used to return from a Machine
Check class interrupt, or as a means of establishing a
new context and synchronizing on that new context
simultaneously.
The contents of MCSRR1 are placed into the MSR. If
the new MSR value does not enable any pending
exceptions, then the next instruction is fetched, under
control of the new MSR value, from the address
MCSRR0 0:61 ||0b00. (Note: VLE behavior may be different;
see Book VLE.) If the new MSR value enables one
or more pending exceptions, the interrupt associated
with the highest priority pending exception is generated;
in this case the value placed into SRR0, CSRR0,
MCSRR0, or DSRR0 [Category: Embedded.Enhanced
Debug] by the interrupt processing mechanism (see
Section 5.6 on page 552) is the address of the instruction
that would have been executed next had the interrupt
not occurred (i.e. the address in MCSRR0 at the
time of the execution of the rfmci).
This instruction is privileged and context synchronizing.
Special Registers Altered:
MSR
Chapter 2. Branch Processor
495