14.06.2015 Views

Power ISA™ Version 2.03 - Power.org

Power ISA™ Version 2.03 - Power.org

Power ISA™ Version 2.03 - Power.org

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

<strong>Version</strong> <strong>2.03</strong><br />

5.9.1.2 Vector Integer Subtract Instructions<br />

Vector Subtract and Write Carry-Out<br />

Unsigned Word<br />

VX-form<br />

Vector Subtract Signed Byte Saturate<br />

VX-form<br />

vsubcuw<br />

VRT,VRA,VRB<br />

vsubsbs<br />

VRT,VRA,VRB<br />

4 VRT VRA VRB 1408<br />

0 6 11 16 21 31<br />

do i=0 to 127 by 32<br />

aop (VRA) i:i+31<br />

bop (VRB) i:i+31<br />

temp (EXTZ(aop) + int EXTZ(¬bop) + int 1) >> 32<br />

VRT i:i+31 temp & 0x0000_0001<br />

For each vector element i from 0 to 3, do the following.<br />

Unsigned-integer word element i in VRB is subtracted<br />

from unsigned-integer word element i in<br />

VRA. The complement of the borrow out of bit 0 of<br />

the 32-bit difference is zero-extended to 32 bits<br />

and placed into word element i of VRT.<br />

Special Registers Altered:<br />

None<br />

4 VRT VRA VRB 1792<br />

0 6 11 16 21 31<br />

do i=0 to 127 by 8<br />

aop EXTS((VRA) i:i+7 )<br />

bop EXTS((VRB) i:i+7 )<br />

VRT i:i+7 <br />

Clamp(aop + int ¬bop + int 1, -128, 127) 24:31<br />

For each vector element i from 0 to 15, do the following.<br />

Signed-integer byte element i in VRB is subtracted<br />

from signed-integer byte element i in VRA.<br />

- If the intermediate result is greater than<br />

127 the result saturates to 127.<br />

- If the intermediate result is less than -128<br />

the result saturates to -128.<br />

The low-order 8 bits of the result are placed into<br />

byte element i of VRT.<br />

Special Registers Altered:<br />

SAT<br />

Vector Subtract Signed Halfword Saturate<br />

VX-form<br />

Vector Subtract Signed Word Saturate<br />

VX-form<br />

vsubshs<br />

VRT,VRA,VRB<br />

vsubsws<br />

VRT,VRA,VRB<br />

4 VRT VRA VRB 1856<br />

0 6 11 16 21 31<br />

do i=0 to 127 by 16<br />

aop EXTS((VRA) i:i+15 )<br />

bop EXTS((VRB) i:i+15 )<br />

VRT i:i+15<br />

Clamp(aop + int ¬bop + int 1, -2 15 , 2 15 -1) 16:31<br />

For each vector element i from 0 to 7, do the following.<br />

Signed-integer halfword element i in VRB is subtracted<br />

from signed-integer halfword element i in<br />

VRA.<br />

- If the intermediate result is greater than<br />

2 15 -1 the result saturates to 2 15 -1.<br />

- If the intermediate result is less than -2 15<br />

the result saturates to -2 15 .<br />

The low-order 16 bits of the result are placed into<br />

halfword element i of VRT.<br />

Special Registers Altered:<br />

SAT<br />

4 VRT VRA VRB 1920<br />

0 6 11 16 21 31<br />

do i=0 to 127 by 32<br />

aop EXTS((VRA) i:i+31 )<br />

bop EXTS((VRB) i:i+31 )<br />

VRT i:i+31 Clamp(aop + int ¬bop + int 1,-2 31 ,2 31 -1)<br />

For each vector element i from 0 to 3, do the following.<br />

Signed-integer word element i in VRB is subtracted<br />

from signed-integer word element i in VRA.<br />

- If the intermediate result is greater than<br />

2 31 -1 the result saturates to 2 31 -1.<br />

- If the intermediate result is less than -2 31<br />

the result saturates to -2 31 .<br />

The low-order 32 bits of the result are placed into<br />

word element i of VRT.<br />

Special Registers Altered:<br />

SAT<br />

158<br />

<strong>Power</strong> ISA -- Book I

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!