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Chapter 4. Branch Operation Instructions
4.1 Branch Processor Registers. . . . . 653
4.1.1 Condition Register (CR). . . . . . . 653
4.1.1.1 Condition Register Setting for
Compare Instructions . . . . . . . . . . . . . 654
4.1.1.2 Condition Register Setting for the
Bit Test Instruction. . . . . . . . . . . . . . . . 654
4.1.2 Link Register (LR) . . . . . . . . . . . 654
4.1.3 Count Register (CTR) . . . . . . . . 654
4.2 Branch Instructions . . . . . . . . . . . . 655
4.3 System Linkage Instructions . . . . . 658
4.4 Condition Register Instructions . . . 661
This section defines Branch instructions that can be
executed when a processor is in VLE mode and the
registers that support them.
4.1 Branch Processor Registers
The registers that support branch operations are:
Section 4.1.1, “Condition Register (CR)”
Section 4.1.2, “Link Register (LR)”
Section 4.1.3, “Count Register (CTR)”
4.1.1 Condition Register (CR)
The Condition Register (CR) is a 32-bit register which
reflects the result of certain operations, and provides a
mechanism for testing (and branching). The CR is
more fully defined in Book I.
Category VLE uses the entire CR, but some comparison
operations and all Branch instructions are limited to
using CR0–CR3. The full Book I condition register field
and logical operations are provided however.
CR
32 63
Figure 17. Condition Register
The bits in the Condition Register are grouped into
eight 4-bit fields, CR Field 0 (CR0) ... CR Field 7 (CR7),
which are set by VLE defined instructions in one of the
following ways.
Specified fields of the condition register can be set
by a move to the CR from a GPR (mtcrf, mtocrf).
A specified CR field can be set by a move to the
CR from another CR field (e_mcrf) or from
XER 32:35 (mcrxr).
CR field 0 can be set as the implicit result of a
fixed-point instruction.
A specified CR field can be set as the result of a
fixed-point compare instruction.
CR field 0 can be set as the result of a fixed-point
bit test instruction.
Other instructions from implemented categories may
also set bits in the CR in the same manner that they
would when not in VLE mode.
Instructions are provided to perform logical operations
on individual CR bits and to test individual CR bits.
For all fixed-point instructions in which the Rc bit is
defined and set, and for e_add2i., e_and2i.,and
e_and2is., the first three bits of CR field 0 (CR 32:34 ) are
set by signed comparison of the result to zero, and the
fourth bit of CR field 0 (CR 35 ) is copied from the final
state of XER SO . “Result” here refers to the entire 64-bit
value placed into the target register in 64-bit mode, and
to bits 32:63 of the value placed into the target register
in 32-bit mode.
if (64-bit mode)
then M 0
else M 32
if (target_register) M:63 < 0 then c 0b100
else if (target_register) M:63 > 0 then c 0b010
else
c 0b001
CR0 c || XER SO
If any portion of the result is undefined, the value
placed into the first three bits of CR field 0 is undefined.
The bits of CR field 0 are interpreted as shown below.
CR Bit Description
32 Negative (LT)
The result is negative.
33 Positive (GT)
The result is positive.
34 Zero (EQ)
The result is 0.
Chapter 4. Branch Operation Instructions
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