Power ISA™ Version 2.03 - Power.org

Version 2.03
Later, if the debug exception has not been reset by
clearing DBSR IAC1 , DBSR IAC2 , DBSR IAC3 , and
DBSR IAC4 , and MSR DE is set to 1, a delayed Debug
interrupt will occur. In this case, CSRR0/DSRR0 [Category:
Embedded.Enhanced Debug will contain the
address of the instruction after the one which enabled
the Debug interrupt by setting MSR DE to 1. Software in
the Debug interrupt handler can observe DBSR IDE to
determine how to interpret the value in CSRR0/DSRR0
[Category: Embedded.Enhanced Debug.
8.4.2 Data Address Compare
Debug Event
One or more Data Address Compare debug events
(DAC1R, DAC1W, DAC2R, DAC2W) occur if they are
enabled, execution is attempted of a data storage
access instruction, and the type, address, and possibly
even the data value of the data storage access meet
the criteria specified in the Debug Control Register 0,
Debug Control Register 2, and the DAC1, DAC2,
DVC1, and DVC2 Registers.
Data Address Compare Read/Write
Enable
DBCR0 DAC1 specifies whether DAC1R debug events
can occur on read-type data storage accesses and
whether DAC1W debug events can occur on write-type
data storage accesses.
DBCR0 DAC2 specifies whether DAC2R debug events
can occur on read-type data storage accesses and
whether DAC2W debug events can occur on write-type
data storage accesses.
Indexed-string instructions (lswx, stswx) for which the
XER field specifies zero bytes as the length of the
string are treated as no-ops, and are not allowed to
cause Data Address Compare debug events.
All Load instructions are considered reads with respect
to debug events, while all Store instructions are considered
writes with respect to debug events. In addition,
the Cache Management instructions, and certain special
cases, are handled as follows.
- dcbt, dcbtls, dcbtep, dcbtst, dcbtstls, dcbtstep,
icbt, icbtls, icbtep, icbi, icblc, dcblc,
and icbiep are all considered reads with
respect to debug events. Note that dcbt,
dcbtep, dcbtst, dcbtstep, icbt, and icbtep
are treated as no-operations when they report
Data Storage or Data TLB Miss exceptions,
instead of being allowed to cause interrupts.
However, these instructions are allowed to
cause Debug interrupts, even when they
would otherwise have been no-op’ed due to a
Data Storage or Data TLB Miss exception.
- dcbz, dcbzep, dcbi, dcbf, dcbfep, dcba,
dcbst, and dcbstep are all considered writes
with respect to debug events. Note that dcbf,
dcbfep, dcbst, and dcbstep are considered
reads with respect to Data Storage exceptions,
since they do not actually change the
data at a given address. However, since the
execution of these instructions may result in
write activity on the processor’s data bus, they
are treated as writes with respect to debug
events.
Data Address Compare User/Supervisor
Mode
DBCR2 DAC1US specifies whether DAC1R and
DAC1W debug events can occur in user mode or
supervisor mode, or both.
DBCR2 DAC2US specifies whether DAC2R and
DAC2W debug events can occur in user mode or
supervisor mode, or both.
Effective/Real Address Mode
DBCR2 DAC1ER specifies whether effective
addresses, real addresses, effective addresses
and MSR DS =0, or effective addresses and
MSR DS =1 are used to in determining an address
match on DAC1R and DAC1W debug events.
DBCR2 DAC2ER specifies whether effective
addresses, real addresses, effective addresses
and MSR DS =0, or effective addresses and
MSR DS =1 are used to in determining an address
match on DAC2R and DAC2W debug events.
Data Address Compare Mode
DBCR2 DAC12M specifies whether all or some of the
bits of the address of the data storage access must
match the contents of the DAC1 or DAC2, whether
the address must be inside a specific range specified
by the DAC1 and DAC2 or outside a specific
range specified by the DAC1 and DAC2 for a
DAC1R, DAC1W, DAC2R or DAC2W debug event
to occur.
There are four data address compare modes.
- Exact address compare mode
If the 64-bit address of the data storage
access is equal to the value in the enabled
Data Address Compare Register, a data
address match occurs.
For 64-bit implementations, the addresses
are masked to compare only bits 32:63 when
the processor is executing in 32-bit mode.
- Address bit match mode
If the address of the data storage access,
ANDed with the contents of the DAC2, are
equal to the contents of the DAC1, also
ANDed with the contents of the DAC2, a data
Chapter 8. Debug Facilities
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