Power ISA™ Version 2.03 - Power.org

Version 2.03
Vector Shift Right
VX-form
Vector Shift Right by Octet
VX-form
vsr
VRT,VRA,VRB
vsro
VRT,VRA,VRB
4 VRT VRA VRB 708
0 6 11 16 21 31
4 VRT VRA VRB 1100
0 6 11 16 21 31
sh (VRB) 125:127
t 1
do i=0 to 127 by 8
t t & ((VRB) i+5:i+7 =sh)
if t=1 then VRT (VRA) >> ui sh
else VRT undefined
The contents of VRA are shifted right by the number of
bits specified in (VRB) 125:127 .
- Bits shifted out of bit 127 are lost.
- Zeros are supplied to the vacated bits on the
left.
The result is place into VRT, except if, for any byte element
in register VRB, the low-order 3 bits are not equal
to the shift amount, then VRT is undefined.
Special Registers Altered:
None
shb (VRB) 121:124
VRT (VRA) >> ui ( shb || 0b000 )
The contents of VRA are shifted right by the number of
bytes specified in (VRB) 121:124 .
- Bytes shifted out of byte 15 are lost.
- Zeros are supplied to the vacated bytes on the
left.
The result is placed into VRT.
Special Registers Altered:
None
Programming Note
A double-register shift by a dynamically specified
number of bits (0-127) can be performed in six
instructions. The following example shifts Vw || Vx
left by the number of bits specified in Vy and places
the high-order 128 bits of the result into Vz.
vslo Vt1,Vw,Vy #shift high-order reg left
vsl Vt1,Vt1,Vy
vsububm Vt3,V0,Vy #adjust shift count ((V0)=0)
vsro Vt2,Vx,Vt3 #shift low-order reg right
vsr Vt2,Vt2,Vt3
vor Vz,Vt1,Vt2 #merge to get final result
154
Power ISA -- Book I