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5.8 Interrupt Ordering and Masking
It is possible for multiple exceptions to exist simultaneously,
each of which could cause the generation of
an interrupt. Furthermore, for interrupts classes other
than the Machine Check interrupt and critical interrupts,
the architecture does not provide for reporting more
than one interrupt of the same class (unless the
Embedded.Enhanced Debug category is supported).
Therefore, the architecture defines that interrupts are
ordered with respect to each other, and provides a
masking mechanism for certain persistent interrupt
types.
When an interrupt is masked (disabled), and an event
causes an exception that would normally generate the
interrupt, the exception persists as a status bit in a register
(which register depends upon the exception type).
However, no interrupt is generated. Later, if the interrupt
is enabled (unmasked), and the exception status
has not been cleared by software, the interrupt due to
the original exception event will then finally be generated.
All asynchronous interrupts can be masked. In addition,
certain synchronous interrupts can be masked. An
example of such an interrupt is the Floating-Point
Enabled exception type Program interrupt. The execution
of a floating-point instruction that causes the
FPSCR FEX bit to be set to 1 is considered an exception
event, regardless of the setting of MSR FE0,FE1 . If
MSR FE0,FE1 are both 0, then the Floating-Point
Enabled exception type of Program interrupt is
masked, but the exception persists in the FPSCR FEX
bit. Later, if the MSR FE0,FE1 bits are enabled, the interrupt
will finally be generated.
The architecture enables implementations to avoid situations
in which an interrupt would cause the state information
(saved in Save/Restore Registers) from a
previous interrupt to be overwritten and lost. In order to
do this, the architecture defines interrupt classes in a
hierarchical manner. At each interrupt class, hardware
automatically disables any further interrupts associated
with the interrupt class by masking the interrupt enable
in the MSR when the interrupt is taken. In addition,
each interrupt class masks the interrupt enable in the
MSR for each lower class in the hierarchy. The hierarchy
of interrupt classes is as follows from highest to
lowest:
Interrupt Class
MSR Enables
Cleared
Save/Restore
Registers
Machine Check ME,DE, CE, EE MSRR0/1
Debug 1 DE,CE,EE DSRR0/1
Critical CE,EE CSRR0/1
Base EE SRR0/1
1 The Debug interrupt class is Category: E.ED.
Note: MSR DE may be cleared when a critical interrupt
occurs if Category: E.ED is not supported.
Figure 16. Interrupt Hierarchy
If the Embedded.Enhanced Debug category is not supported
(or is supported and is not enabled), then the
Debug interrupt becomes a Critical class interrupt and
all critical class interrupts will clear DE, CE, and EE in
the MSR.
Base Class interrupts that occur as a result of precise
exceptions are not masked by the EE bit in the MSR
and any such exception that occurs prior to software
saving the state of SRR0/1 in a base class exception
handler will result in a situation that could result in the
loss of state information.
This first step of the hardware clearing the MSR enable
bits lower in the hierarchy shown in Figure 16 prevents
any subsequent asynchronous interrupts from overwriting
the Save/Restore Registers (SRR0/SRR1, CSRR0/
CSRR1, MCSRR0/MCSRR1, or DSRR0/DSRR1 [Category:
Embedded.Enhanced Debug]), prior to software
being able to save their contents. Hardware also automatically
clears, on any interrupt,
MSR WE,PR,FP,FE0,FE1,IS,DS . The clearing of these bits
assists in the avoidance of subsequent interrupts of
certain other types. However, guaranteeing that interrupt
classes lower in the hierarchy do not occur and
thus do not overwrite the Save/Restore Registers
(SRR0/SRR1, CSRR0/CSRR1, DSRR0/DSRR1 [Category:
Embedded.Enhanced Debug], or MCSRR0/
MCSRR1) also requires the cooperation of system software.
Specifically, system software must avoid the execution
of instructions that could cause (or enable) a
subsequent interrupt, if the contents of the Save/
Restore Registers (SRR0/SRR1, CSRR0/CSRR1,
DSRR0/DSRR1 [Category: Embedded.Enhanced
Debug]), or MCSRR0/MCSRR1) have not yet been
saved.
Chapter 5. Interrupts and Exceptions
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