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Version 2.03
2.3 Branch Processor Instructions
2.4 System Linkage Instructions
These instructions provide the means by which a program
can call upon the system to perform a service,
and by which the system can return from performing a
service or from processing an interrupt.
The System Call instruction is described in Book I, but
only at the level required by an application programmer.
A complete description of this instruction appears
below.
System Call
SC-form
Return From Interrupt
XL-form
sc
rfi
17 /// /// /// /// // 1 /
0 6 11 16 20 27 30 31
SRR0 iea CIA + 4
SRR1 MSR
NIA IVPR 0:47 || IVOR8 48:59 || 0b0000
MSR new_value (see below)
The effective address of the instruction following the
System Call instruction is placed into SRR0. The contents
of the MSR are copied into SRR1.
Then a System Call interrupt is generated. The interrupt
causes the MSR to be set as described in Section
5.6 on page 552.
The interrupt causes the next instruction to be fetched
from effective address
IVPR 0:47 ||IVOR8 48:59 ||0b0000.
This instruction is context synchronizing.
Special Registers Altered:
SRR0 SRR1 MSR
19 /// /// /// 50 /
0 6 11 16 21 31
MSR SRR1
NIA iea SRR0 0:61 || 0b00
The rfi instruction is used to return from a base class
interrupt, or as a means of simultaneously establishing
a new context and synchronizing on that new context.
The contents of SRR1 are placed into the MSR. If the
new MSR value does not enable any pending exceptions,
then the next instruction is fetched, under control
of the new MSR value, from the address
SRR0 0:61 ||0b00. (Note: VLE behavior may be different;
see Book VLE.) If the new MSR value enables one or
more pending exceptions, the interrupt associated with
the highest priority pending exception is generated; in
this case the value placed into the applicable save/
restore register 0 by the interrupt processing mechanism
(see Section 5.6 on page 552) is the address of
the instruction that would have been executed next had
the interrupt not occurred (i.e. the address in SRR0 at
the time of the execution of the rfi).
This instruction is privileged and context synchronizing.
Special Registers Altered:
MSR
Chapter 2. Branch Processor
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